XpressSWITCH for USB4

PCIe® Switch IP for USB4 Hubs, Hosts and Devices

XpressSWITCH™ for USB4® is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully configurable fanout switch, XpressSWITCH for USB4 provides one upstream port and up to 31 downstream ports. XpressSWITCH for USB4 enables designers to support tunneling of PCIe traffic in USB4 Hubs as mandated by the USB4 specification, and is also an ideal addition to USB4 Devices or Hosts for attaching internal or external PCIe devices. By implementing internal PCIe devices, designers can differentiate their USB4 ICs while reducing latency and power consumption. XpressSWITCH for USB4 provides a flexible, scalable and configurable PCIe switching solution for USB4 Hubs, Hosts and Devices.

Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements. XpressSWITCH for USB4 controller IP is integrated, validated, and silicon-proven with a variety of PHY IP spanning PCIe 1.1 through 5.0, and process nodes as small as 7nm. Supported combos include PHY IP from our PHY Partner Ecosystem.

Contact us for more information.

PCI Express (PCIe) is a complex protocols, and PLDA recognizes that our customers may not always have internal expertise, resources, or the time required to meet their development schedules. Our Advanced Design Integration (ADI) team helps these customers shorten their development cycle by providing expert services in the following areas:

  • Integration of commercial and proprietary PCIe PHY IP
  • Development and validation of custom PCIe PCS layer
  • Customization of the PCIe IP to add customer-specific features
  • Generation of custom reference designs
  • Generation of custom verification environments
  • Check out our Integration Services page for more information on our ADI team and its capabilities

Check out our Integration Services page for more information on our ADI team and its capabilities.

  • Xilinx UltraScale+ series: up to PCIe Gen4 x8 on each port
  • Intel 10 series (Arria, Stratix): up to PCIe Gen3 x8 on each port
  • Prior generation device families (ex. Intel PSG [Altera] V-series, Xilinx 7-series) can be supported upon request

We are actively working with Intel and Xilinx to offer an integrated solution for PCIe 5.0 at 32GT/s on leading edge FPGA.

PCI Express Interfaces (upstream and downstream ports) 

  • Designed to the USB4 Specification v1.0 
  • Follows PCIe 1.0 protocol, but can operate at any compatible speed 
  • 1 upstream port, up to 31 downstream ports 
  • Supports PCIe Base Revision 5.0, backward compatible down to 3.1 
  • Supports PHY Interface for PCIe (PIPE) 5.x 
  • Single Virtual Channel (VC) implementation 
  • Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit) 
  • Configurable Receive and Replay buffer sizes 
  • Advanced Error Reporting (AER) supported on each port 
  • ECRC generation and check 
  • LTR, ACS, FPB, PTM, Hot Plug enabled per USB4 Specification mandate for Hubs 
  • Lane reversal supported 
  • Switch upstream port supports multiple physical functions 
  • Supports for in-the-flow processing 
  • ASPM L1, L2 
  • Clock and Power gating 
  • Peer-to-peer communication between downstream ports 


Switching Logic

  • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets 
  • L1 and wake-up events forwarding 
  • Peer-to-Peer transactions support between downstream ports 
  • Broadcast and Multicast supported 
  • Downstream Port Containment (DPC and eDPC) supported 
  • Round-Robin arbitration 
  • No Packet buffering (cut-through architecture) for reduced latency 
  • Built-in advanced data protection including ECRC, LCRC, ECC and Parity 
  • Test port available for switch logic monitoring 
  • Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic 

  • Fully transparent design eliminates the need for Host configuration and management software
  • Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
  • Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
  • Lowest latency switching logic on the market (2 clock cycles)
  • Architecture allows insertion of custom processing in-the-flow (i.e. filtering, encryption, etc.)
  • The only solution that supports Hot Plug

The XpressSWITCH for USB4 Controller IP is integrated and thoroughly verified using a combination of commercial and homegrown VIP and testsuites. PLDA makes extensive use of FPGAs for hardware validation, and has developed tools and software to help with system-level validation.

Our rigorous verification and validation process ensure customers can focus on the core of their application.

IP files​

  • Verilog RTL source code
  • Libraries for functional simulation
  • Configuration assistant GUI (Wizard)

Verification Environment


Reference Design

  • Synthesizable Verilog RTL source code
  • Simulation environment and test scripts
  • Synthesis project & constraint files