PCIe 5.0, 4.0, 3.1/3.0 Switch Fabric IP Core Supporting up to 32 Root/Hosts, 32 Endpoint/Devices, Built-in NTB
XpressSWITCH-MRB is a customizable and fully configurable Fabric Switch IP for PCIe designed for ASIC and FPGA implementations that enables high-performance communication between multiple hosts or root complexes and one or more devices or endpoints. XpressSWITCH-MRB is a self-contained Fabric Switch IP implemented entirely in RTL logic; it does not require any external Fabric Manager or Management Host nor does it implement any embedded CPU. Once configured via the integrated Fabric Manager, the PCIe Fabric Switch IP enables sharing of every endpoint resources such as PFs or VFs among all available hosts, using device drivers natively provided by the Operating Systems running on each host. XpressSWITCH-MRB optionally implements Non-Transparent Bridging (NTB) functionality, allowing every host to communicate with each other and to support failover mechanisms. By implementing XpressSWITCH-MRB into their SoCs, designers have a flexible, configurable, self-contained solution for PCIe Fabric switching with multi-host to multi-device connectivity that is ultra low latency, low power, and O/S and platform agnostic.
- Xilinx UltraScale+ series: up to Gen4 x8 or Gen3 x16 on each port
- Altera 10 series (Arria, Stratix): up to Gen4 x8 or Gen3 x16 on each port
- Older device families (ex. Altera V-series, Xilinx 7-series) can be supported upon request
Note that the number of ports that can be implemented on FPGA is limited by the number of transceivers/quads available on the targeted device.
Contact us for IP availability.
XpressSWITCH-MRB can be used in a variety of applications, including but not limited to, sharing of NVMe SSDs across multiple Hosts or sharing of network bandwidth (NIC sharing) across multiple Hosts.
#1 Shared NVMe Storage #2 Shared Network Bandwidth
- Up to 32 Host connections (upstream ports)
- Up to 32 Device connections (downstream ports)
- Limited to 31 if Hot Plug is enabled
- Supports PCIe 5.0, 4.0, or 3.1 on each port and up to 16 lanes
- Can have different PCIe speed and #lanes on each port
- Optional Hot Plug support on downstream ports
- Per-PF or per-VF sharing of device resources among available hosts
- Optional Non-Transparent Bridging (NTB) allowing communication between hosts
- NTB via doorbells, scratchpad registers and messaging
- Transparent switch design does not require host-specific device driver or software; connected devices are recognized and can be operated via OS-provided drivers
- Self-contained implementation does not require any external "Control Host" or "Fabric Manager", limiting complexity and reducing point of failures
- Full RTL logic implementation without the use of built-in CPU for simplified implementation and optimal performance