PCIe 5.0, 4.0, 3.1/3.0 Multi-port Transparent Switch IP Core with 1 Upstream Port and up to 31 Downstream Ports
XpressSWITCH is a customizable, multiport embedded Switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and multiple downstream ports and fully configurable. XpressSWITCH is the first embedded switch IP available on the market and enables designers to use fewer PCIe PHYs, saving latency, power consumption and bill-of-material. The PCIe switch IP transparently manages upstream-downstream data flow as well as peer-to-peer transfers between downstream ports, delivering the flexibility, scalability and configurability required for connecting multiple devices, including NVMe SSDs.
XpressSWITCH controller IP is integrated, validated, and silicon-proven with a variety of PCIe PHY IP covering PCIe 5.0, 4.0 3.1, 2.1, 1.1, and process nodes down to 7nm. Supported combos include PHY IP from our Partner Ecosystem, PHY IP from EDA vendors Synopsys and Cadence, PHY IP from leading edge ASIC vendors, and integrated PHY Hard IP from FPGA vendors Intel (Altera) and Xilinx.
Some of our proven PCIe 5.0, 4.0 and 3.1 Controller-PHY combos include:
- Analog Bits PHY on TSMC 16FF
- ASIC Vendor "A" PHY on TSMC 28, 16FF, 7FF
- Cadence PHY on TSMC 28
- GUC PHY on TSMC 28, 16FF, 12FF
- Intel PSG Stratix 10, Arria 10 integrated PHY
- M31 PHY on SMIC 40
- Phison PHY on TSMC 28HPC+, UMC 28
- Rambus PHY on TSMC 28
- Synopsys PHY on UMC 28HPC+, TSMC 7FF
- VSemi (Intel) PHY on UMC 40, Intel 32, UMC 28
- Xilinx Virtex UltraScale/UltraScale+ integrated PHY
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
PCI Express is a complex protocol, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities.
- Xilinx UltraScale+ series : up to Gen4 x8 on each port
- Altera 10 series (Arria, Stratix): up to Gen4 x8 on each port
- Older device families (ex. Altera V-series, Xilinx 7-series) can be supported upon request
We are actively working with Intel PSG and Xilinx to offer an integrated solution for PCIe 5.0 at 32GT/s on leading edge FPGA.
Note that the number of ports that can be implemented on FPGA is limited by the number of transceivers/quads available on the targeted device.
PCI Express Interfaces (upstream and downstream ports)
- 1 upstream port, up to 31 downstream ports
- Up to x16 link width per port
- Link rate of 2.5, 5.0, 8.0, 16, and 32 Gbps per lane (Gen1, Gen2, Gen3, Gen4, Gen5 rates)
- PCI Express Base Specification Revision 5.0, 4.0 and 3.1 compliant
- PHY Interface for PCI Express (PIPE) 5.x compliant
- Single Virtual Channel (VC) implementation
- Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit) for embedded endpoints
- Configurable Receive and Replay buffer sizes
- Advanced Error Reporting (AER) supported on each port
- ECRC generation and check
- ARI supported
- Lane reversal supported
- Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port
- Switch upstream port supports multiple physical functions
- Support for Hot Plug on every downstream port
- PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
- L1 and wake-up events forwarding
- Peer-to-Peer transactions support between downstream ports
- Broadcast and Multicast supported
- Downstream Port Containment (DPC) supported
- Round-Robin arbitration
- No Packet buffering (cut-through architecture) for reduced latency
- Built-in advanced data protection including ECRC, LCRC, ECC and Parity
- Test port available for switch logic monitoring
- Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic
- Fully transparent design eliminates the need for Host configuration and management software
- Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
- Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
- Lowest latency switching logic on the market (2 clock cycles)
- Architecture allows insertion of custom processing in-the-flow (i.e. filtering, encryption, etc.)
- The only solution that supports Hot Plug
XpressSWITCH switch IP is integrated and extensively verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, and Mentor VIP, PCIe testsuites, and PLDA-developed verification environment to achieve optimal coverage. Wrappers for these verification environments are available to customers for easy VIP integration.
We use state-of-the-art FPGA prototyping platforms built in-house and from 3rd-party providers to thoroughly validate XpressSWITCH IP in real world conditions.
XpressSWITCH IP is PCI-SIG certified since 2016 and often used as an interoperability host platform for PCIe compliance testing during PCI-SIG workshops.
Our rigorous verification and validation process ensures customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- PCI Express® Windows x64 and Linux x64 device drivers
- PCIe C API
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)