XpressRICH-AXI Controller IP for PCIe 5.0
XpressRICH-AXI Controller IP for PCIe 5.0
Controller IP for PCIe 5.0, 4.0, 3.1/3.0 Supporting Root Port, Endpoint, Dual-mode Configurations, with Optional Built-in DMA and Configurable AMBA AXI Interconnect
XpressRICH-AXI™ is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH-AXI Controller IP for PCIe 5.0 is compliant with the PCI Express 5.0, 4.0, and 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including number, type, and width of AXI interfaces, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. Users may optionally enable the built-in legacy DMA engine, or connect a DMA engine externally such as PLDA's vDMA-AXI DMA, depending on the application requirements. PLDA is working hand in hand with multiple PHY IP vendors and Verification IP vendors to offer a range of integrated solutions for PCIe 5.0 at 32GT/s. PLDA XpressRICH-AXI Controller IP for PCIe 5.0 is the #1 choice for ASIC, SoC and FPGA designers looking for an enterprise-class PCIe interface solution with a high-performance, reliable, and scalable AMBA 3 AXI/AMBA 4 AXI interconnect.
We are actively working with our PHY ecosystem partners to provide an integrated and validated PCIe 5.0 controller + 32G PHY solution on a variety of process nodes and for a variety of foundries, as well as on leading edge FPGAs from Intel PSG and Xilinx.
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
PCI Express is a complex protocol, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities
We are actively working with Intel PSG and Xilinx to offer a path for PCIe 5.0 implementation on leading edge FPGA.
PCI Express layer
- Compliant with the PCI Express 5.0 rev. 0.9 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8-, 16-, 32- and 64-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode configurations
- Supports x16, x8, x4, x2, x1 at Gen5, Gen4, Gen3, Gen2, Gen1 speeds
- Supports up to 32 Physical Functions (PF), 512 Virtual Functions (VF)
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
- Additional optional features include LTR, L1 PM substates, etc.
AMBA AXI layer
- Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
- Supports multiple, user-selectable AXI interfaces including AXI Master, AXI Slave, AXI Stream
- Each AXI interface data width independently configurable in 512-, 256-, 128-, and 64-bit
- Each AXI interface can operate in a separate clock domain
- Supported Burst types include INCR, FIXED, WRAP
- Narrow transfers supported
- Optional built-in Legacy DMA engine
- Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
- Completion reordering, interrupt and descriptor reporting
- Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication
Download the product brief or request the reference manual for complete specification and additional information.
- Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link max. speed and width for reduced gate count and optimal throughput
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code - Gen5 support pending
- Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
- Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
- Availability of multiple AXI Master interfaces, a key benefit for high end SSD to maximize throughput
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
The XpressRICH-AXI controller IP for PCIe 5.0 is integrated and thoroughly verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, Mentor VIP, PCIe testsuites, and a PLDA-developed verification environment to achieve optimal coverage.
Our rigorous verification process ensure customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- PCI Express® Windows x64 and Linux x64 device drivers
- PCIe C API
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)