PCIe 5.0, 4.0, 3.1/3.0 Root Port, Endpoint, Dual-mode, Switch Port Controller IP Core with Native User Interface
XpressRICH5 is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH5 IP is compliant with the PCI Express 5.0 rev.0.7, 4.0, and 3.1/3.0 specifications, as well as with version 5.x of the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. PLDA is working hand in hand with multiple PHY IP vendors and Verification IP vendors to offer a range of integrated solutions for PCIe 5.0 at 32GT/s. PLDA XpressRICH5 PCIe IP is the #1 choice for ASIC, SoC and FPGA designers looking for an enterprise-class PCIe interface solution with a high-performance, low-latency, and flexible user interface allowing for a variety of use models.
We are actively working with our PHY ecosystem partners to provide an integrated and validated PCIe 5.0 controller + 32G PHY solution on a variety of process nodes and for a variety of foundries, as well as on leading edge FPGAs from Intel PSG and Xilinx.
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
PCI Express is a complex protocol, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities.
We are actively working with Intel PSG and Xilinx to offer a path for PCIe 5.0 implementation on leading edge FPGA.
PCI Express layer
- Compliant with the PCI Express 5.0 rev.0.7 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 5.x (8-, 16-, 32-, and 64-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x16, x8, x4, x2, x1 at Gen5, Gen4, Gen3, Gen2, Gen1 speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
- Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
User Interface layer
- 512-bit or 256-bit transmit/receive low-latency user interface
- Up to 2 TLP per clock cycle (TLP chaining)
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Download the product brief or request the reference manual for complete specification and additional information.
- Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) allows implementation of custom credit management schemes in the application logic
- Merged Replay and Transmit buffer enables lower memory footprint
- Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
The XpressRICH5 controller IP is integrated and thoroughly verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, Mentor VIP, PCIe testsuites, and a PLDA-developed verification environment to achieve optimal coverage.
Our rigorous verification process ensure customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- PCI Express® Windows x64 and Linux x64 device drivers
- PCIe C API
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)