XpressRICH3-AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH3-AXI IP is compliant with the PCI Express 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including number, type, and width of AXI interfaces, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. Users may optionally enable the built-in Legacy DMA engine based on the application requirements. XpressRICH3-AXI IP is verified using multiple PCIe VIPs and testsuites, and is proven in production silicon in hundreds of designs using a variety of commercial and proprietary PCIe PHYs. PLDA XpressRICH3-AXI PCIe IP is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
XpressRICH3-AXI controller IP is integrated, validated, and silicon-proven with a variety of PCIe PHY IP covering PCIe 3.1, 2.1, 1.1, and process nodes down to 7nm. Supported combos include PHY IP from our Partner Ecosystem, PHY IP from EDA vendors Synopsys and Cadence, PHY IP from leading edge ASIC vendors, and integrated PHY Hard IP from FPGA vendors Intel (Altera) and Xilinx.
Some of our proven PCIe 3.1 Controller-PHY combos include:
- Analog Bits PHY on TSMC 16FF
- Avago PHY on TSMC 28, 16FF, 7FF
- Cadence PHY on TSMC 28
- GUC PHY on TSMC 28, 16FF, 12FF
- Intel PSG Stratix V, Stratix 10, Arria 10 integrated PHY
- M31 PHY on SMIC 40
- Phison PHY on TSMC 28HPC+, UMC 28
- Rambus PHY on TSMC 28
- Synopsys PHY on UMC 28HPC+, TSMC 7FF
- VSemi (Intel) PHY on UMC 40, Intel 32, UMC 28
- Xilinx Virtex-7, Virtex UltraScale integrated PHY
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
PCI Express is a complex protocol, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities
- Xilinx 7-series and UltraScale series: up to Gen3 x8
- Xilinx UltraScale+ series : up to Gen3 x16
- Altera V-series (Arria, Stratix): up to Gen3 x8
- Altera 10 series (Arria, Stratix): up to Gen3 x16
Note that the number of ports that can be implemented on FPGA is limited by the number of transceivers/quads available on the targeted device.
PCI Express layer
- Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode configurations
- Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
- Supports many ECNs including LTR, L1 PM substates, etc.
AMBA AXI layer
- Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
- Supports multiple, user-selectable AXI interfaces including AXI Master, AXI Slave, AXI Stream
- Each AXI interface data width independently configurable in 256-, 128-, and 64-bit
- Each AXI interface can operate in a separate clock domain
- Built-in Legacy DMA engine
- Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
- Completion reordering, interrupt and descriptor reporting
- Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication
Download the product brief or request the reference manual for complete specification and additional information.
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen3 x16 with same RTL code
- Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
- Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
- Availability of multiple AXI Master interfaces, a key benefit for high end SSD to maximize throughput
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
The XpressRICH3-AXI controller IP is integrated and thoroughly verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, and Mentor VIP, PCIe testsuites, and PLDA-developed verification environment to achieve optimal coverage.
We use state-of-the-art FPGA prototyping platforms built in-house and from 3rd-party providers to thoroughly validate XpressRICH3-AXI IP in real world conditions.
XpressRICH3-AXI IP is multiple times PCI-SIG certified.
Our rigorous verification process ensure customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- PCI Express® Windows x64 and Linux x64 device drivers
- PCIe C API
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)