XpressRICH Controller IP for PCIe 3.1/3.0
XpressRICH Controller IP for PCIe 3.1/3.0
Controller IP for PCIe 3.1/3.0 Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations, with Native User Interface
XpressRICH is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH Controller IP for PCIe 3.x is compliant with the PCI Express 3.1/3.0 specification, as well as with the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. XpressRICH Controller IP is verified using multiple PCIe VIPs and testsuites, and is proven in production silicon in hundreds of designs using a variety of commercial and proprietary PCIe PHYs. PLDA XpressRICH Controller IP for PCIe 3.1/3.0 is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
We are actively working with our PHY ecosystem partners to provide an integrated and validated PCIe 3.0 controller + 8G PHY solution on a variety of process nodes and for a variety of foundries, as well as on leading edge FPGAs from Intel PSG and Xilinx.
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
PCI Express is a complex protocol, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities.
- Xilinx 7-series and UltraScale series: up to Gen3 x8
- Xilinx UltraScale+ series : up to Gen3 x16
- Altera V-series (Arria, Stratix): up to Gen3 x8
- Altera 10 series (Arria, Stratix): up to Gen3 x16
Note that the number of ports that can be implemented on FPGA is limited by the number of transceivers/quads available on the targeted device.
PCI Express layer
- Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
- Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
User Interface layer
- 256-bit transmit/receive low-latency user interface
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Download the product brief or request the reference manual for complete specification and additional information.
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen3 x16 with same RTL code
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
- Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
- Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
XpressRICH controller IP for PCIe 3.1/3.0 is integrated and extensively verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, and Mentor VIP, PCIe testsuites, and PLDA-developed verification environment to achieve optimal coverage.
We use state-of-the-art FPGA prototyping platforms built in-house and from 3rd-party providers to thoroughly validate XpressRICH IP in real world conditions.
XpressRICH IP is multiple times PCI-SIG certified.
Our rigorous verification and validation process ensure customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- PCI Express® Windows x64 and Linux x64 device drivers
- PCIe C API
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)