XpressRICH Controller IP for PCIe 6.0
XpressRICH Controller IP for PCIe 6.0
Controller IP for PCIe 6.0, Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with Native User Interface
XpressRICH™ Controller IP for PCIe® 6.0 is a configurable and scalable PCIe controller Soft IP designed for ASIC implementation. The XpressRICH Controller IP for PCIe 6.0 supports the PCIe® 6.0 specification, including 64GT/s data rates, PAM4, FLIT mode, and L0p power state, as well as version 6.x of the PHY Interface for PCI Express (PIPE) specification. Backwards compatible to the PCIe 5.0, 4.0, and 3.1/3.0 specifications, XpressRICH for PCIe 6.0 exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.
The PCIe 6.0 architecture will be essential for SoC designers creating next generation chips that require the movement of large amounts of data within systems, including applications like HPC/Cloud Computing, Artificial Intelligence (AI), Machine Learning, Enterprise Storage & Networking, and Automotive. As a proven leader in PCIe controller design, PLDA ensures that our IP provides our customers high performance, ease-of-integration and first-pass silicon success.
- Flexible architecture supports a variety of use cases, tailored to unique customer needs.
- Scalable 256/512/1024-bit data path.
- Advanced PIPE modes and port bifurcation.
- Supports many optional PCIe 6.0 features and ECNs.
- Optional PHY integration allowing customers to confidently select the PCIe 6.0 PHY IP that best fits their requirements.
- Demonstrated 2 GHz operation on 5 nm process node.
- Optimized application interface for increased bandwidth efficiency.
- Built-in RAS: supports advanced reliability, availability, and serviceability features.
- Optional IDE security with AES-GCM encryption, decryption & authentication.
- Hundreds of customers, ASIC/SoC tape-outs, and FPGA designs since PCIe 1.1.
- Stringent verification methodology and validation.
- Demonstrated interoperability with processor makers, PHY and VIP vendors.
PCI Express is a complex protocol, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities.
PCI Express layer
- Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8-, 16-, 32-, 64- and 128-bit) specifications
- Supports SerDes Architecture PIPE 10b/20b/40b/80b width
- Supports Original PIPE 8b/16b/32b/64b/128b width
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x1 to x16 architectures at PCIe 6.0 to PCIe 1.0 speeds
- Supports Forward Error Correction (FEC) - Lightweight algorithm for low latency
- Supports L0p Low Power mode
- Up to 4-bit parity protection for data path
- Supports Clock Gating and Power Gating
- RAS features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
User Interface layer
- Native 256-/512-/1024-bit Tx/Rx interface
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Integrity and Data Encryption (IDE) - Optional
- Implements the PCI Express IDE ECN
- Configurable IDE engine
- Supports x1 to x16 lanes
- Configurable data bus for PCIe IDE
- Configurable pipeline stages for difference process nodes for best cost and performance balance
- Supports containment and skid modes
- Supports multi-stream
- Utilizes high-performance AES-GCM for encryption, decryption, authentication
- PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
- PCIe IDE automatic IDE prefix insertion and detection
- PCIe IDE automatic IDE sync/fail message generation
- PCRC calculation & validation
- Efficient key control/refresh
- Bypass mode
- Internal data path size automatically scales up or down (256-, 512-, 1024- bits) based on max. link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) allows implementation of custom credit management schemes in the application logic
- Merged Replay and Transmit buffer enables lower memory footprint
- Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
- Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
The XpressRICH controller IP for PCIe 6.0 is integrated and thoroughly verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, Mentor VIP, PCIe testsuites, and a PLDA-developed verification environment to achieve optimal coverage.
Our rigorous verification process ensure customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
- IP Reference Manual
- Getting Started Guide
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)