XpressLINK-SOC Controller IP for CXL

Compute Express Link Controller IP Designed to the CXL Link Specification with Configurable AMBA AXI Interconnect

XpressLINK-SOC™ is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. The XpressLINK-SOC Controller IP leverages PLDA's silicon proven XpressRICH-AXI Controller for PCIe 5.0 architecture for the CXL.io path, and adds the CXL.cache and CXL.mem paths specific to CXL. XpressLINK-SOC supports the AMBA® AXI™ Protocol Specification for CXL.io traffic, and either Intel CXL-cache/mem Protocol Interface (CPI) or a AMBA® AXI™ Protocol Specification for CXL.mem and CPI interface for CXL.cache traffic, or the ARM CXS.B Protocol Specification. XpressLINK-SOC also complies with the Intel PHY Interface for PCI Express (PIPE) specification version 5.x and supports the PIPE LPC and SERDES modes. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power. XpressLINK-SOC is extensively verified using commercial as well as homegrown VIP and testsuites, and has been integrated with a number of PCIe 5.0 PHY IP. 

XpressLINK-SOC controller IP supports a variety of PCIe 5.0 PHY IP, including PHY IP from our PHY Partner Ecosystem.

Contact us for more information.

PCI Express and CXL are complex protocols, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:

  • Integration of commercial and proprietary PCIe PHY IP
  • Development and validation of custom PCIe PCS layer
  • Customization of the Controller IP to add customer-specific features
  • Generation of custom reference designs
  • Generation of custom verification environments

Check out our Integration Services page for more information on our ADI team and its capabilities.

We are working with Intel and Xilinx to offer a path for CXL/PCIe 5.0 soft IP implementation on leading edge FPGA. 

CXL Protocol Layer

  • Supports the latest CXL specification
  • Backward compatible with CXL 1.1 specification
  • Implements the CXL.io, CXL.mem, and CXL.cache protocols
  • Supports all 3 defined CXL device types
  • Supports the PCI Express 5.0 base specification revision 1.0
  • Supports the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface width
  • Supports CXL device configurations
  • Supports operation at x16, x8, x4, x2, x1
  • Supports Host, Device, Switch ports and Dual Mode/shared silicon implementation
  • Supports Low-latency CXL.mem flit encoder/decoder
  • Supports Viral error containment
  • Supports deferrable writes
  • Supports Standard Intel CPI interface or AMBA AXI for CXL.mem
  • Supports Standard Intel CPI interface for CXL.cache
  • Supports ARM CXS.B interface
  • Supports Sync header bypass and drift buffer modes supported
  • Supports All low-power states
  • Supports CXL RAS features (including Viral and Data Poisoning)
  • Supports Hot-Plug
  • Supports Alternate Protocol Negotiation
  • Supports RCiEP

AMBA AXI Layer for CXL.io

  • Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
  • Optional AXI4-Lite Slave interface for Bridge Configuration
  • Optional AXI4-Lite Master interface for External Registers Configuration
  • Optional AXI4 Master Descriptor interface to access SG-DMA Descriptors in AXI domain
  • Up to 4 AXI4 Master interfaces, each supporting up to 128 outstanding read requests
  • Up to 4 AXI4 Slave interfaces, each supporting up to 256 outstanding read requests
  • Up to 4 AXI4 Stream Input and Output interfaces, each handling up to 8 TID/TDEST combinations simultaneously
  • 64-bit, 128-bit, 256-bit, or 512-bit data support for AXI4 Master, Slave, and Stream interfaces
  • Bypassable CDC for AXI4 Master, Slave, and Stream interfaces
  • AXI4 Master and Slave interfaces can be configured as AXI3 interfaces
  • Optional built-in Legacy DMA engine
    • Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
    • Completion reordering, interrupt and descriptor reporting
  • Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication

Download the product brief or request the reference manual for complete specification and additional information.

  • Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
  • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
  • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
  • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
  • Ultra-low Transmit and Receive Buffer latency 
  • Use of highly optimized CPI interface for CXL.cache and CXL.mem to maximize throughput and minimize latency 
  • Merged Replay and Transmit buffer enables lower memory footprint
  • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

The XpressLINK-SOC controller IP is integrated and thoroughly verified using a combination of commercial and homegrown VIP and testsuites. We make extensive use of FPGA for hardware validation, and we have developed tools and software to help with system-level validation.

Our rigorous verification and validation process ensure customers can focus on the core of their application.

IP files​

  • Verilog RTL source code
  • Libraries for functional simulation
  • Configuration assistant GUI (Wizard)

Verification Environment

Documentation

Reference Design

  • Synthesizable Verilog RTL source code
  • Simulation environment and test scripts
  • Synthesis project & constraint files