XpressLINK Controller IP for CXL 2.0/1.1

Controller IP for the Compute Express Link (CXL) Specification supporting CXL.io, CXL.cache, CXL.mem

XpressLINK™ is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA's silicon proven XpressRICH Controller for PCIe 5.0 architecture for the CXL.io path, and adds the CXL.cache and CXL.mem paths specific to CXL. XpressLINK exposes PLDA native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic. XpressLINK also complies with the Intel PHY Interface for PCI Express (PIPE) specification version 5.x. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power. XpressLINK is extensively verified using commercial as well as homegrown VIP and testsuites, and has been integrated with a number of PCIe 5.0 PHY IP. 

XpressLINK controller IP supports a variety of PCIe 5.0 PHY IP, including PHY IP from our PHY Partner Ecosystem.

Contact us for more information.

PCI Express and CXL are complex protocols, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:

  • Integration of commercial and proprietary PCIe PHY IP
  • Development and validation of custom PCIe PCS layer
  • Customization of the Controller IP to add customer-specific features
  • Generation of custom reference designs
  • Generation of custom verification environments

Check out our Integration Services page for more information on our ADI team and its capabilities.

We are working with Intel and Xilinx to offer a path for CXL/PCIe 5.0 soft IP implementation on leading edge FPGA. 

CXL layer

  • Supports the CXL 2.0 specification
  • Backward compatible with CXL 1.1 specification
  • Implements the CXL.io, CXL.mem, and CXL.cache protocols
  • Supports all 3 defined CXL device types
  • Supports Host, Device, Switch ports and Dual Mode/shared silicon implementation
  • Supports the PCI Express 5.0 base specification revision 1.0
  • Supports the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface width
  • Supports CXL device configurations
  • Supports operation at x16, x8, x4, x2, x1
  • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
  • Supports up to 64 Physical Functions (PF), 512 Virtual Functions (VF)
  • Supports PCI Express Advanced Error Reporting (AER)
  • Supports optional ECNs
  • Supports Port Bifurcation
  • Supports deferrable writes
  • Supports DOE, CMA over DOE

User Interface layer

  • PLDA native 256/512-bit transmit/receive low-latency interface for CXL.io traffic
  • Intel-defined CXL cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic
  • User-selectable Transaction/Application Layer clock frequency (CXL.io)
  • Dedicated sideband interface for Reliability, Availability and Serviceability (RAS) features

Integrity and Data Encryption (IDE)

  • AES-GCM security supports CXL.mem/CXL.cache at full line rate and with zero latency
  • AES-GCM security IP supports PCIe/CXL.io to near full line rate with low latency
  • Implements the CXL 2.0 IDE specifications for CXL.cache/mem
  • Implements the PCI Express IDE ECN for CXL.io
  • Configurable IDE engine
    • Supports x1 to x16 lanes
    • Supports all device types  
    • 256-bit or 512-bit data bus for PCIe IDE
    • 512-bit data bus for CXL.cache/mem IDE
  • Supports containment and skid modes
  • Supports early MAC termination
  • Supports multi-stream
  • Utilizes high-performance AES-GCM for encryption, decryption, authentication
  • PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
  • PCIe IDE automatic IDE prefix insertion and detection
  • PCIe IDE automatic IDE sync/fail message generation
  • PCRC calculation & validation
  • Efficient key control/refresh
  • Bypass mode

Download the product brief or request the reference manual for complete specification and additional information.

  • Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
  • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
  • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
  • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
  • Ultra-low Transmit and Receive Buffer latency 
  • Use of highly optimized CPI interface for CXL.cache and CXL.mem to maximize throughput and minimize latency 
  • Smart buffer management on receive side (Rx Stream) allows implementation of custom credit management schemes in the application logic
  • Merged Replay and Transmit buffer enables lower memory footprint
  • Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
  • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

The XpressLINK controller IP is integrated and thoroughly verified using a combination of commercial and homegrown VIP and testsuites. We make extensive use of FPGA for hardware validation, and we have developed tools and software to help with system-level validation.

Our rigorous verification and validation process ensure customers can focus on the core of their application.

IP files​

  • Verilog RTL source code
  • Libraries for functional simulation
  • Configuration assistant GUI (Wizard)

Verification Environment


Reference Design

  • Synthesizable Verilog RTL source code
  • Simulation environment and test scripts
  • Synthesis project & constraint files