XpressCCIX Controller IP for PCIe 5.0 with CCIX Extension
XpressCCIX Controller IP for PCIe 5.0 with CCIX Extension
Controller IP for PCIe 5.0, 4.0, 3.1/3.0 Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations, with CCIX ESM Support and Native User Interface
XpressCCIX™ is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressCCIX Controller IP supports the PCI Express 5.0, 4.0 and 3.1/3.0 specifications, as well as with version 4.x and 5.x of the PHY Interface for PCI Express (PIPE) specification, and supports the CCIX Extended Speed Mode as defined in the CCIX Base Specification Revision 1.1. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CCIX ESM mode, data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. XpressCCIX IP is verified using multiple PCIe VIPs and testsuites, and integrated with select CCIX 20G/25G compatible PHYs. PLDA XpressCCIX Controller IP for PCIe 5.0 with CCIX ESM support is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
We are actively working with our PHY ecosystem partners to provide an integrated and validated PCIe 5.0 controller + 32G PHY solution on a variety of process nodes and for a variety of foundries, as well as on leading edge FPGAs from Intel PSG and Xilinx.
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
PCI Express and CCIX are complex protocols, and customers may not always have the expertise, the resources, or the time required to meet their development schedule. Our Advanced Design Integration (ADI) team helps customers shorten their development cycle by proposing expert services in the following areas:
- Integration of commercial and proprietary PCIe/CCIX PHY IP
- Development and validation of custom PCIe PCS layer
- Customization of the PCIe/CCIX IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
Check out our Integration Services page for more information on our ADI team and its capabilities.
We are actively working with Intel PSG and Xilinx to offer a path for PCIe 5.0/CCIX 32G implementation on leading edge FPGA.
PCI Express layer
- Supports the PCI Express 5.0, 4.0, 3.1/3.0, and PIPE 4.x (8-, 16-, 32- and 64-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x16, x8, x4, x2, x1 at 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
- Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
- Implements DVSEC Capability as per CCIX Base Specification Rev. 1.0
- Supports CCIX ESM DataRate0 at 20 Gb/s and DataRate1 at 25 Gb/s
User Interface layer
- 512-bit transmit/receive low-latency user interface
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Download the product brief or request the reference manual for complete specification and additional information.
- Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when multi-function or SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8, Gen3 x16, CCIX 25G x8 with same RTL code (when supported)
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
- Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
- Optional Transaction Layer bypass allows for customer-developed application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
The XpressCCIX controller IP is integrated and thoroughly verified using multiple VIP for foolproof reliability. We use a combination of Avery VIP, Cadence VIP, and Mentor VIP, PCIe testsuites, and PLDA-developed verification environment to achieve optimal coverage.
We use state-of-the-art FPGA prototyping platforms built in-house to thoroughly validate XpressCCIX IP in real world conditions.
Our rigorous verification process ensure customers can focus on the core of their application.
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
PCI Express® Bus Functional Model
- Encrypted Simulation libraries
- PCI Express® Windows x64 and Linux x64 device drivers
- PCIe C API
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)