vDMA Many-Channel Centralized DMA Controller with AMBA AXI Interconnect Optimized for AI/ML SoCs, Virtualized Environments
The vDMA-AXI IP Core implements a highly efficient, configurable DMA engine specifically engineered for Artificial Intelligence (AI) optimized SoCs and FPGAs that power tomorrow’s virtualized data centers. The vDMA-AXI IP is intended to be used as a centralized DMA allowing concurrent data movement in any direction, and is particularly suited for many-core SoCs such as AI and ML processors. The vDMA-AXI IP Core is based on a novel architecture that allows hundreds of independent and concurrent DMA channels to be distributed among a number of Virtual Machines (VMs) or host domains without sacrificing on performance and resource utilization. The vDMA-AXI IP is optimized to deliver the highest possible throughput for small data packet transfers, which is a common weakness in traditional DMA engines. The vDMA-AXI IP can optionally be attached externally to PLDA’s XpressRICH-AXI PCIe controller IP for PCIe 5.0 for a scalable enterprise class PCIe interface solution for compute, network, and storage SoCs.
VDMA-AXI is controlled through a set of registers accessible from the AXI4-Lite interface. The register map is extensively described in the VDMA-AXI reference manual. To help with software development, a PCIe device driver is available along with a C API, and demonstrates VDMA-AXI operation when connected externally to a PCIe interface such as PLDA's XpressRICH-AXI controller IP for PCIe 5.0. The PCIe device driver is available for Linux x64 and Windows x64.
- Xilinx UltraScale, UltraScale+ series
- Altera 10 series (Arria, Stratix)
Looking for help integrating our vDMA-AXI IP? Our Advanced Design Integration (ADI) team is here to help shorten your development cycle by proposing expert services in the following areas:
- Customization of the vDMA IP to add customer-specific features or enhance existing features
- Generation of custom reference designs
- Generation of custom verification environments and testsuites
- Help with bring-up and performance tuning
Check out our Integration Services page for more information on our ADI team and its capabilities
- Up to 256 DMA channels
- Up to 6 Virtual Machines or domains
- Configurable AMBA AXI3/4 interfaces with 256-bit or 512-bit data path
- Up to 64 outstanding read and write requests
- Dynamically reconfigurable DMA channel Source and Destination
- Scatter-Gather DMA with dynamic DMA control per descriptor
- Circular queues for packet transmission and reception
- Fetching of up to 256 descriptors for optimized throughput
- Optional DMA channels Descriptor reporting for simplified software management
- Centralized DMA channel Context Memory for reduced footprint
QoS and Security Features
- Round robin fair bandwidth sharing between channels
- Configurable packet size for bandwidth sharing
- Non-blocking DMA channel operation
- Domain Isolation enforced with sideband signaling for identification and access control
The vDMA-AXI DMA controller IP is integrated and thoroughly verified using Mentor VIP for foolproof reliability.
Our rigorous verification process ensure customers can focus on the core of their application.
- Synthesizable Verilog RTL (source code or encrypted source code)
- Software Design Kit
- Linux device driver (binary or source code)
- C API
- vDMA-AXI IP user's manual