vDMA Many-Channel Centralized DMA Controller with AMBA AXI Interconnect Optimized for AI SoCs, Virtualized Environments

The vDMA-AXI IP Core implements a highly efficient DMA engine specifically engineered for Artificial Intelligence (AI) optimized SoCs that power tomorrow’s virtualized data centers. The vDMA-AXI IP is intended to be used as a centralized DMA allowing concurrent data movement in any direction, and is particularly suited for many-core SoCs such as AI processors. The vDMA-AXI IP Core is based on a novel architecture that allows thousands of independent and concurrent DMA channels to be distributed among a number of Virtual Machines (VMs) or domains without sacrificing on performance and resource utilization. The vDMA-AXI IP is also available pre-integrated with PLDA’s SR-IOV enabled XpressRICH-AXI PCIe controller IP for PCIe 5.0 for a scalable enterprise class PCIe interface solution for compute, network, and storage SoCs.

VDMA-AXI is controlled through a set of registers accessible from the AXI4-Lite interface. The register map is extensively described in the VDMA-AXI reference manual. To help with software development, a PCIe device driver is available along with a C API, and demonstrates VDMA-AXI operation when connected to a PCIe interface. The PCIe device driver is available for Linux x64 and Windows x64. Refer to our XpressRICH-AXI controller IP for PCIe 5.0 for an integrated PCIe+vDMA solution.

  • Xilinx UltraScale, UltraScale+ series
  • Altera 10 series (Arria, Stratix)

Looking for help integrating our vDMA-AXI IP? Our Advanced Design Integration (ADI) team is here to help shorten your development cycle by proposing expert services in the following areas:

  • Customization of the vDMA IP to add customer-specific features
  • Generation of custom reference designs
  • Generation of custom verification environments
  • Help with bring-up and performance tuning

Check out our Integration Services page for more information on our ADI team and its capabilities

General/Performance Features

  • Up to 2048 DMA channels
  • Up to 512 Virtual Machines or domains
  • Configurable AMBA AXI3/4 interfaces with 256-bit or 512-bit data path
  • Up to 128 outstanding read and write requests
  • Dynamically reconfigurable DMA channel Source and Destination
  • Scatter-Gather DMA with dynamic DMA control per descriptor
  • Circular queues for packet transmission and reception
  • Fetching of up to 128 descriptors for optimized throughput
  • Optional DMA channels Descriptor reporting for simplified software management
  • Centralized DMA channel Context Memory for reduced footprint

Security Features

  • Data path and Context memory protected with CRC and Parity bits
  • VM Isolation enforced with sideband signaling for identification and access control
  • Optional ECC protection for Context memory

QoS Features

  • Round robin fair bandwidth sharing between channels
  • Configurable packet size for bandwidth sharing
  • Non-blocking DMA channel operation through proprietary mechanism

The vDMA-AXI DMA controller IP is integrated and thoroughly verified using Mentor VIP for foolproof reliability.

Our rigorous verification process ensure customers can focus on the core of their application.

  • Synthesizable Verilog RTL (source code or encrypted source code)
  • Software Design Kit
    • Linux device driver (binary or source code)
    • C API
  • vDMA-AXI IP user's manual