PCIe 4.0 Endpoint Reference Platform for Prototyping and Development of PCIe 4.0 Root Port/Host Silicon and Devices

PLDA Gen4ENDPOINT is a PCIe add-in card suitable for prototyping and developing PCIe 4.0 hardware and software. At the core of Gen4ENDPOINT is PLDA's PCI-SIG compliant XpressRICH4™ controller IP for PCIe 4.0 technology running on a Xilinx® Virtex® UltraScale+™ FPGA. Gen4ENDPOINT features as an integrated PCIe 4.0 endpoint agent with DMA and memory-mapped I/O capability. By working with Gen4ENDPOINT, early developers of PCIe 4.0 host systems and root complexes can accelerate their software, firmware, and hardware developments, in their production environment, using the Operating System of their choosing.

PCIe 4.0 Host/Root Complex testing

  • Silicon validation engineers can test their PCIe 4.0 Hosts or Root Complexes by initiating DMA transfers from Gen4ENDPOINT or utilizing Gen4ENDPOINT's memory-mapped address space for testing direct MMIO transfers
  • Software engineers can develop and test system firmware such as BIOS with an actual PCIe 4.0 compliant endpoint that implements all the required PCIe 4.0 Configuration Space registers

Gen4ENDPOINT is based on a Xilinx Virtex UltraScale+ XCVU3P-1FFVC1517E FPGA and features:

  • A PCIe 4.0 x8 add-in card, enabling testing x1, x4, or x8* lanes at up to Gen4 (16GT/s) speed

  • Factory programmed with PLDA endpoint reference design enabling up to PCIe 4.0 x8* link training, configuration space access, and traffic generation via DMA

  • Can be plugged directly to the host/motherboard, or via the Gen4HOST reference platform for adding a transparent switch in the PCIe hierarchy


* See Product Versions section for detail.

  • Ready to use Gen4ENDPOINT Platform (pre-loaded firmware)
  • PLDA driver and traffic generator GUI software (provided for Windows x64)
  • Getting Started manual
  • Technical support and maintenance updates

Model PCIe Max. Link Speed PCIe Max. Link Width
48 Gen4 16GT/s x8