Gen-Z 1.0 Controller IP

Gen-Z Controller IP Compliant to the Gen-Z Core Specification 1.0 and PHY Specification 1.0

PLDA Gen-Z Controller IP Core is a highly scalable and configurable semiconductor IP core compliant to the Gen-Z Core Specification 1.0 and Gen-Z PHY Specification 1.0, and suitable for both component-side and host-side implementation. The controller integrates multiple requesters, mutiple responders, and multiple link interfaces (Zlink), interconnected together through a switch interconnect. At the user interface level, the Gen-Z Controller IP offers a low latency, variable width AMBA 3/4 AXI interface. The Gen-Z controller can optionally be configured to implement PLDA vDMA many-channel DMA engine as well as a ZMMU for supporting complex address translation and memory management. At the PHY level, PLDA is working with our PHY Partners to offer a complete, pre-integrated and validated interfacing solution for Gen-Z on various process nodes and foundries, as well as on leading edge FPGA devices. 

We are actively working with our PHY ecosystem partners to provide an integrated and validated Gen-Z controller + PHY solution on a variety of process nodes and for a variety of foundries, as well as on leading edge FPGAs from Intel PSG and Xilinx. 

Our roadmap includes support of both PCIe PHYs at 16 GT/s and 32 GT/s and IEEE 802.3 PHYs at 25 GT/s, 56 GT/s and 112 GT/s .

Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.

The Gen-Z controller IP is integrated and thoroughly verified using multiple verification environments for foolproof reliability. We use a combination of Avery Gen-Z VIP, HPE Gen-Z testbenches and testsuites, and a PLDA-developed verification environment to achieve optimal coverage.

Our rigorous verification process ensure customers can confidently concentrate on the core of their application.

  • Up to 16 Requesters
  • Up to 16 Responders
  • Up to 64 Link interfaces with aggregation support
  • Configurable AMBA user interface datapath: 64-bit to 1024-bit
  • Independent clock domain for each interface
  • In-band and out-of-band configuration and management
  • Explicit (Core 64, Control, Atomic 1, LDM1) and Implicit (P2P 64) OpClasses
  • Up to 32 Virtual Channels with VC remapping and up to 32 VC Actions
  • Up to 16 Traffic Classes
  • Up to 4096 subnets per system
  • Multicast​
  • Multipath routing with LPRT, SSDT and RIT routing tables
  • Multi-Subnet support with MPRT and MSDT routing tables
  • Link-Level Reliability (LLR)
  • Non-Idempotent Request (NIR)
  • Packet data integrity
  • Interrupts, Hot Plug, Power Management support
  • Configurable PLA interface datapath: 32-bit to 4096-bit
  • Asymmetric Rx/Tx datapath support