Gen-Z 1.0 Controller IP
Gen-Z 1.0 Controller IP
Gen-Z Controller IP Compliant to the Gen-Z Core Specification 1.0a and PHY Specification 1.0a
PLDA Gen-Z Controller IP Core is a highly scalable and configurable semiconductor IP core compliant to the Gen-Z Core Specification 1.0a and Gen-Z PHY Specification 1.0a, and suitable for both media-side and host-side implementation. The controller integrates multiple requesters, mutiple responders, and multiple Zlink, interconnected together through a switch core. At the user interface level, the Gen-Z Controller IP offers an ultra-low latency, variable width AMBA 3/4 AXI interface. The Gen-Z controller can optionally be configured to implement PLDA vDMA many-channel DMA engine as well as a ZMMU for supporting complex address translation and memory management. At the PHY level, PLDA is working with our PHY Partners to offer a complete, pre-integrated and validated interfacing solution for Gen-Z on various process nodes and foundries, as well as on leading edge FPGA devices.
PLDA Gen-Z Controller IP is co-developed with Gen-Z Consortium founding member HPE.
We are actively working with our PHY ecosystem partners to provide an integrated and validated Gen-Z controller + PHY solution on a variety of process nodes and for a variety of foundries, as well as on leading edge FPGAs from Intel PSG and Xilinx.
Our roadmap includes support of both PCIe PHYs up to 32 GT/s (NRZ) and PAM4 PHYs at 56 GT/s and 112 GT/s.
Our unmatched expertise in PHY integration means customers can confidently select the PHY IP that best fit their requirements.
The Gen-Z controller IP is integrated and thoroughly verified using multiple verification environments for foolproof reliability. We use a combination of Avery Gen-Z VIP, HPE originated Gen-Z testbenches and testsuites, and a PLDA-developed verification environment to achieve optimal coverage.
Our rigorous verification process ensures customers can confidently concentrate on the core of their application.
- Up to 4 Requesters and 4 Responders
- Dedicated user interface per path
- Multi-VC support
- Variable width interface: 128-, 256-, 512-bit
- AMBA AXI3/4 interfaces, AXI4-Lite for control/status
- Integrated Gen-Z Switch
- Up to 4 Zlink
- Link aggregation/splitting
- Asymmetric Tx/Rx support
- Optional built-in ZMMU
- Optional built-in many-channel DMA
- ECC on every SRAM
- Gen-Z specification 1.0a compliant
- Gen-Z PHY specification 1.0a compliant
- Explicit and P2P Classes support
- Non-Idempotent Request (NIR) support incl. Atomic OpClass
- Link-Level Retry support
- Logical PCI Device (LPD)/PECAM support
- Out-of-band management support through APB (AXI4-Lite) I/F
- In-band management support including Unsolicited Events and Directed Packet Relay