What ADI Team Can Do For You

Implementing high-speed interconnect protocols in ASICs, SoCs and FPGAs is not an easy task, and you may not always have the expertise, the resources, or the time required to meet your development schedule.

Our Advanced Design Integration (ADI) group is a dedicated team of engineers within PLDA with the mission to help you shorten your SoC/ASIC/FPGA development cycles by offering expertise and services around the PLDA IP or product you are integrating.

Our ADI team areas of expertise include pre-silicon activities such as RTL design, integration, verification, project consulting, training, and post-silicon activities such as silicon bring-up, hardware validation and debug, compliance preparation.

Add-on Modules: Development of custom add-on modules for the Controller IP, such as clock/reset management module, AXI bridge layer, monitoring/debug module, etc.

IP Customization: Customization of Controller IP to incorporate new features or tweaking of existing features, such as optional PCIe features/ECNs, optional PIPE features, custom AXI-PCIe ordering rules, custom arbitration for Switch, etc.

PCS for PCIe: Development of custom PCS layers for PLDA PCIe IP, for proprietary PHY, non-PIPE compliant PHY, etc.

Reference Designs: Customization of existing reference designs or development of new reference designs for the IP, such as MSI-X, SR-IOV, DMA, etc.

Testbenches: Development of application-specific testbenches, such as hotplug BFM, etc.

PCIe PHY integration & validation: Integration of proprietary or commercial PHY, development of port bifurcation wrappers, deployment of PLDA PHY interop testbench & testsuite

PCIe VIP integration: Deployment of simulation environment (suport for Avery, Cadence, Mentor, and PLDA VIPs), adaptation to customer-specific IP configuration

Verification of custom IP configurations: Development of custom test cases, utilization of PLDA “Verification Factory”, support for Avery, Cadence, Mentor, and PLDA VIPs

Consulting: Design/architecture review and RTL signoff, review of clock & reset implementation, review of power-up sequencing, review of IP configuration parameters, review of recovery mechanisms, review of low power management, etc.

Protocol Training: Training on PCIe and other protocols via our dedicated training entity: www.pldatraining.com

PCIe PHY test chip validation: Building a reference design for testing a PHY test chip with PLDA PCIe controller using FPGA.

PCIe device bring-up and diagnostic: Using PLDA Inspector for device diagnostic during power-up, link testing, low power testing, stress testing, etc.

PCI-SIG workshop preparation: Preparing for PCI-SIG Compliance testing, including PTC, electrical, PCIECV, Gold, and Interop tests.

The ADI Team

 

  •  Dedicated engineering team
  •  Combined 20 years expertise in IC design
  •  Covering RTL design, verification, hardware, ASIC, FPGA, software
  •  Engineers in US and EU
  •  Possibility of on-site intervention
  •  Time-based and fixed-price service contracts
  •  PLDA IT infrastructure and EDA tools

 

Contact us