PLDA is organizing a FREE 1-day technical event for designers who want to learn about PCIe Design and Integration in SoCs
After attending this event, Designers will be able to:
- Integrate commercial or home-grown PCIe PHY IP into their SoCs, and use a PHY Testsuite to identify and debug PHY issues at PIPE interface level
- Integrate a 3rd-party PCIe VIP, perform application-level verification, identify and troubleshoot reported issues, and assess the need for regression automation
- Bring up, test, and validate their PCIe 4.0 endpoint devices, and quickly identify and debug link-level and functional-level issues
The number of seats is limited, so don't wait to register!