PCIe 4.0 Controller and PHY Provide Complete IP Solution Enabling Early Adopters of the Emerging PCIe 4.0 Specification to Accelerate Product Development and Reduce Integration Risk. See a demonstration at The TSMC Symposium in San Jose on April 7th.
Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, Advanced Error Reporting (AER) and more
Using the same silicon-proven IP found in PLDA’s XpressRICH3 product, PLDA’s PCIe 4.0 controller IP and Bus Functional Model (BFM) enable SoC and ASIC designers to quickly incorporate PCIe 4.0. PLDA provides testing and integration with third party PHYs, delivering a complete and flexible PCIe 4.0 solution.