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Verification IP Partner

PLDA and Verification IP partners collaborate to prequalify PCIe IP controller with VIP to enhance quality of the PCIe solution. The results of this technical collaboration is improved chip design and verification quality, along with an easier and more robust design flow. Mutual customers can shave months of effort and time off their design and verification cycles and get their products to market faster.

Avery supports over 35 standard protocols ranging from high speed IO, SSD/HDD, mobile, embedded storage, memory, and control bus protocols.  Avery VIPs offer the most complete verification solutions consisting of SystemVerilog UVM compliant models and environment, protocol checkers, directed and random compliance test suites, and reference verification frameworks.  Advanced debug features include multi-level analyzer trackers to visualize data and control flow through the protocol stacks.  Compliance verification services are offered for all VIPs.

The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF. The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Platform; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

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