Senior Designer ASIC / Architect

Location: to be determined

Your mission:

You will join the R&D team under the responsibility of the Design Team Manager, your mission will be to:

• Define architecture and implement RTL design in accordance with specifications and requirements
• Collaborates and communicates with management regarding design status, project progress and issue resolution
• Ensures the designs meet quality, performance, schedule, and cost goals
• Provide customer level 3 technical support for the implemented design
• Provide guidance and mentoring to less experienced staff members
• Provide proper documentation of design architecture and definition, and support for the final product documentation

Skills requirement:

• ASIC and FPGA design flow
• Verilog logic design
• Proficiency in programming and/or scripting languages (Python, Cshell…)
• Knowledge on High speed interface protocols, High Speed Serdes and PHY PMA
• Good English skills, communication skills, and willingness to work with an international team
• High speed interface protocols (PCIe, Gen-Z, …)
• High performance computing system, processor, cache coherency, chipset and ASICs

Your profile:

• Master's degree or PHD in Electrical Engineering, Computer engineering or equivalent.
• 10 or more years of experience in ASIC or FPGA design.

Please send your application to jobs@plda.com

ASIC / FPGA Design Engineer

Location: Aix-en-Provence, France

Your role: 

As part of the R&D team under the responsibility of the Design Manager, your role will be to:

• Define the architecture and implement the RTL design of IP blocks that comply with the given specifications and requirements
• Guarantee the quality and performance of your design
• Collaborate with Management and keep them informed of the progress of your activities, your results, and any unseen problems
• Respect the project schedule and its budget
• Provide level 3 support for the implemented design
• Document architectural and design work, and provide the necessary elements for product documentation

Required Skills: 

• Mastery of the ASIC and FPGA development process
• Mastery of RTL design in Verilog
• Good level of English and general communication, comfortable with international team work

Additional Desirable Skills: 

• In-depth experience in the field of high-speed interface protocols (PCIe, Gen-Z, etc), Serdes, and PHY PMAs​
• Solid experience in the field of "High performance computing", cache coherence, and SOCs

Your profile:

• 5 or more years of experience in ASIC or FPGA design

Please send your application to jobs@plda.com

Verification Engineer

Location: to be determined

Your mission:

You will join the R&D team under the responsibility of the Director of Engineering and Verification Team Leader, your mission will be to:

• Guaranty RTL designs are matching specifications and requirements
• Define and implement verification plans and test plans to ensure the designs meet quality and performance goals
• Build and maintain automated verification environments
• Collaborates and communicates with management regarding verification status, project progress, and issue resolution
• Provide customer level 3 technical support for the implemented design
• Provide guidance and mentoring to less experienced staff members
• Provide proper and comprehensive documentation for the usage and the architecture of the verification environments as well as reports for the verification results
• Contribute to technical directions on all aspects of the verification domain

Skills requirement:

• Verilog, System Verilog
• Verification EDA tools, Verification methodologies, Verification IPs
• Data management and version control systems
• Automation servers and continuous integration
• Proficiency in programming and/or scripting languages (Python, Cshell…)
• Knowledge on High speed interface protocols (PCIe, Gen-Z …), Serdes and PHY PMA
• Background in digital circuitry or hardware logic design
• Good English skills, communication skills, and willingness to work with an international team.

Your profile:

• Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
• 3 or more years of experience in ASIC or FPGA design.

Please send your application to jobs@plda.com

Stage Réf. 2020.1 / Ingénieur 3ème année

Conception et prototypage sur FPGA d'un module logique RTL de diagnostic embarqué

Localisation : Aix-en-Provence, France

Dans le cadre de ses activités de R&D, PLDA développe des IP logiques pour le protocole standard d’interconnexion PCIe.  PLDA innove avec une technologie appelée « Inspector » qui permet d’effectuer des opérations de diagnostic et de corriger le comportement du contrôleur PCIe depuis l’intérieur du système. Vous serez en charge de la conception d’un module logique embarqué « Inspector » et de son prototypage sur FPGA.

Objectifs du stage :

• Etude du protocole PCIe
• Design et vérification d’un module logique « Inspector » rattaché au module contrôleur PCIe
• Portage du design logic sur FPGA
• Expérimentation, analyse des résultats et optimisation

Disciplines abordées :

• Design RTL en langage Verilog
• Simulation logique
• Outils de portage sur FPGA
• Méthodes de vérification et validation
• Software embarqué

Outils et langages :

• FPGA
• Verilog, SystemVerilog
• Simulateur logique
• Python
• Anglais technique indispensable

Merci d'envoyer votre CV à jobs@plda.com

Stage Réf. 2020.2 / Ingénieur 3ème année

Conception et intégration d'un modèle logique de simulation d'interface AXI

Localisation : Aix-en-Provence, France

Dans le cadre de ses activités de R&D, PLDA développe des IP logiques pour les protocoles standards d’interconnexion PCIe et Gen-Z. Afin de s’interconnecter facilement dans les System On Chip (SOC), les modules logiques utilisent le protocole d’interface standard AXI comme défini par Arm. Vous serez en charge de la conception du modèle logique de simulation pour l’interface AXI et de son intégration dans les environnements de test des différents produits.

Objectifs du stage :

• Etude du protocole AXI
• Design et vérification du modèle logique de simulation pour le protocole AXI
• Intégration et vérification du modèle de simulation dans les différents environnements de test
• Expérimentation, analyse des résultats et optimisation

Disciplines abordées :

• Design en langage System Verilog
• Simulation logique
• Méthodes de vérification et validation

Outils et langages :

• Verilog, SystemVerilog
• Simulateur logique
• Python
• Anglais technique indispensable

Merci d'envoyer votre CV à jobs@plda.com