Junior Design & Verification Engineer - ADI

Aix-en-Provence, France - Full-time

About PLDA

PLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, CXL, and Gen-Z. PLDA has established itself as a leader in that space with over 3,200 customers and 6,400 licenses in 62 countries. PLDA is a global technology company with offices in Silicon Valley, France, Bulgaria, Taiwan, and China.

Your Mission

You will join the AD&I team, your mission will be to:

  • Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY IP
  • Verifying the RTL design with dedicated simulation environment
  • Test cases development
  • Support worldwide customers on the IP integration
  • Track and maintain your productivity metrics
  • Reporting periodically on progress and difficulties

Skills Requirement

Positive and self-driven achiever with:

  • "Can Do" Attitude
  • Strong analytical and problem solving skills
  • Excellent interpersonal skills
  • Open for traveling abroad
  • Capable to handle calls with customers.
  • Work in international organization and specially with teams in France, ASIA & USA
  • Because PLDA operates internationally, very good English is important for the position.

Your Profile

  • Bachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplines

Your technical experience:

  • 2-5 years of experience in RTL design & verification with Verilog/SystemVerilog
  • Experience in ASIC or FPGA
  • Experience with UVM
  • Experience in multinational company
  • Experience with creating documentation, python, shell & etc.