PLDA, the industry leader in PCI Express® interface IP solutions, today announced a full set of solutions allowing designers to create products optimized for PCIe® 4.0 now. PCIe 4.0 motherboards are not expected to be obtainable until 2017, but when they become available, the market will expect access to applications and components that can take advantage of PCIe 4.0’s speed and agility. By helping with project solutions now, PLDA enables designers to take advantage of the PCIe 4.0 market with less design lag.
The race to launch devices supporting PCIe 4.0 started several months back. Designers face several challenges to release the product on D-Day:
PLDA and Epostar to Demonstrate New PCIe/NVMe Solution, Delivering the Increased Throughput and Decreased Latency Required for Today’s PCIe SSD Storage Applications
PLDA, the industry leader in PCI Express® interface IP solutions today announces a demonstration of the industry’s first development platform for PCIe® 4.0
SAN JOSE, Calif., June 28, 2016 -- PLDA, the industry leader in PCI Express® interface IP solutions today announces a demonstration of the industry’s first development platform for PCIe® 4.0. This exclusive demonstration can be viewed in PLDA’s booth at PCI-SIG DevCon, being held in Santa Clara, California on June 28-29, 2016.
ASIC Designers and Project Managers can explore the industry’s best suite of tested, silicon-proven, third-party PCIe solutions in one place.
SAN JOSE, Calif., June 6, 2016 -- PLDA, the industry leader in PCI Express® interface IP solutions today announced a focus on their extensive PLDA Ecosystem Partners at their booth during the DAC 2016 show to be held June 6 – 8, 2016 in Austin, Texas. In addition to showcasing their broad selection of PCIe and interface IP, PLDA is providing information on how ASIC designers can accelerate their time-to-market through easy-to-integrate and tested PCIe solutions using the PLDA Ecosystem.
PLDA, the industry leader in PCI Express® interface IP solutions today announced the industry’s first full PCIe 4.0 platform with the launch of the PLDA Gen4SWITCH.
SAN JOSE, Calif., June 21, 2016 -- PLDA, the industry leader in PCI Express® interface IP solutions today announced the industry’s first full PCIe 4.0 platform with the launch of the PLDA Gen4SWITCH. Early adopters of PCI Express 4.0 technology can view the demo of this new PCIe 4.0 platform at the PLDA booth, during PCI-SIG® DevCon to be held on June 28-29, 2016 in Santa Clara, CA.
PLDA Switch IP for PCIe is a customizable and scalable switch design intended to be embedded into ASIC, SoC, and FPGA. PCIe® architecture has become a standard in the enterprise space due to the advantages it provides in term of performance and reliability. Embedding a configurable PCIe switch IP into chip designs provides developers with extra flexibility, scalability and reliability when interconnecting multiple PCIe devices, with significant gains in term of latency and power consumption compared to ASSP solutions.
PLDA Announces XpressSWITCH™ - The Industry’s First Compliant PCI Express® Multiport Embedded Switch IP
XpressSWITCH is an exclusive IP that provides switching logic along with one upstream and multiple embedded or external downstream ports and is optimized for FPGA and ASIC designs.
SAN JOSE, Calif., February 18, 2016 -- PLDA, the industry leader in PCI Express® controller IP solutions, today announced their new XpressSWITCH™ customizable multiport embedded switch IP for FPGA and ASIC designs. PLDA’s XpressSWITCH has achieved PCI Express (PCIe®) compliance based on interoperability testing during the recent PCI-SIG® Compliance Workshop in December 2015.
PLDA’s PCIe Switch Solution provides a customizable and scalable switch design tailored for the needs of the PCIe switch marketplace. The PCIe® architecture has become a standard within the storage data centers due to the advantages it delivers in latency and performance. PCIe switches manage dataflow within a device, delivering the flexibility, scalability and configurability required to connect a large pool of drives or networks.
In that presentation, Rabih Eid, Support Manager, explains how to take advantage of PCIe Embedded Switch technology, reducing BOM, reusing existing designs, decreasing system power consumption and improving overall performance compared to an ASSP device.
Visit PLDA's PCIe Switch IP page for more information.
Methods to Fine-Tune Power Consumption of PCIe devices
A basic paradox of electronic evolution is the desire to enable the execution of more functions while consuming less power and silicon area. For PCIe® applications, this goal is not a new one. A PCI power management specification has been available since 1997, and PCI Express® has featured native power management since its initial release in 2002. In addition, there has always been a recognized need for low power in the mobile market.