In this video, we talk about the PLDA XpressRICH IP wizard which has been designed to enable PCIe designers to easily configure their PCIe controller as required for their application.
PLDA, the industry leader in PCI Express® IP and interconnect solutions, today announced a major PCIe 5.0 design win on cutting edge 5nm process node. PLDA’s PCIe 5.0 Controller IP was selected not only for its solid design and unmatched compatibility with popular PCIe PHYs, but also for PLDA’s best-in-class tech support, its ease of customization and PLDA’s integration expertise.
Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.
In this article, we look into the various protocols by providing a brief history, a quick technical comparison, and the latest deployment status. We also offer our perspective on the evolution of these protocols.
PLDA, the industry leader in PCI Express® interface IP solutions, today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP. PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency. This level of performance is highly anticipated by developers of leading edge applications in Artificial Intelligence (AI) and Machine Learning (ML), data center storage and networking, and High Performance Computing (HPC).