PLDA and AnalogX Announce Market-leading CXL 2.0 Solution featuring Ultra-low Latency and Power

 

Highlights:

  • Optimized integration of PLDA CXL 2.0 controller and AnalogX ultra low power PHY reduces latency by over 50% and power by 40% compared to leading competitive solutions
  • Improves system performance at no extra cost, while pre-configured integration reduces design time and speeds time-to-market

PLDA, the leading developer of high-speed interconnect silicon IP, and AnalogX, the leading provider of low power multi-standard connectivity SerDes IP solutions, today announced an optimized integration of PLDA CXL™ 2.0 controller and AnalogX 32G-MR PHY that reduces latency by 50% and power consumption by 40% compared to leading competitive solutions. 

PLDA Announces XpressLINK-SOC™ CXL Controller IP with Support for the AMBA CXS Issue B Protocol

PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDA’s industry-leading XpressLINK-SOC™ CXL IP provides full support for the AMBA® CXS Issue B (CXS-B) interface protocol. This support enables SoC designers to reduce latency and more easily implement the CXL and CCIX multichip interconnect standards in their Arm®-based System-on Chip (SoC) solutions.

AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller. Using a CXS interface, the designer can bypass the controller’s transaction layer, which can significantly reduce latency. The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink™ Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets. 

PLDA Announces the Successful CXL™ Interoperability with pre-production Intel Xeon CPU, Code Named Sapphire Rapids

PLDA XpressLINK™ CXL Controller IP combines the industry’s lowest latency implementation with an easy-to-integrate design, accelerating adoption of CXL in SoC designs.

 

PLDA, the industry leader in high-speed interconnect solutions, today announced the successful CXL™ interoperability with pre-production Intel Xeon processors code named Sapphire Rapids. The session was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. It resulted in demonstrated interoperability between PLDA’s XpressLINK™ CXL IP, running on a PLDA FPGA-based add-in card, and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors.