PLDA, Aldec and Avery joinly present and demonstrate a new PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA's PCIe 5.0 XpressRICH features include automatic datapath scaling, configurable pipelining (enabling optimal solutions in both ASIC and FPGA), RX Stream mode for custom credit management, L1 PM substrates, dynamically adjustable application clock frequency and clock/power gating.
PLDA® Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect
PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication.
In this video, we walk through the PLDA XpressRICH-AXI™ IP wizard.
PLDA XpressRICH-AXI Controller IP is the #1 choice for ASIC, SoC and FPGA designers looking for an enterprise-class PCIe interface solution with a high-performance, reliable, and scalable AMBA 3 AXI/AMBA 4 AXI interconnect.
PLDA, the industry leader in PCI Express® IP and interconnect solutions, today announced a major PCIe 5.0 design win on cutting edge 5nm process node. PLDA’s PCIe 5.0 Controller IP was selected not only for its solid design and unmatched compatibility with popular PCIe PHYs, but also for PLDA’s best-in-class tech support, its ease of customization and PLDA’s integration expertise.
In this video, we show how SoC designers can leverage the vDMA engine built into PLDA’s XpressRICH-AXI PCIe controller to manage concurrent high performance data traffic between a virtualized PCIe device and multiple Virtual Machines running on the host platform.
Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.
In this article, we look into the various protocols by providing a brief history, a quick technical comparison, and the latest deployment status. We also offer our perspective on the evolution of these protocols.
PLDA, the industry leader in PCI Express® interface IP solutions, today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP. PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency. This level of performance is highly anticipated by developers of leading edge applications in Artificial Intelligence (AI) and Machine Learning (ML), data center storage and networking, and High Performance Computing (HPC).
PCI-SIG Developers Conference 2017, Santa Clara, CA. – June 7, 2017 - PCI-SIG®, the organization responsible for the widely adopted PCI Express® (PCIe®) industry-standard input/output (I/O) technology, today announced 32GT/s as the next progression in speed for the PCIe 5.0 architecture, targeting high-performance applications such as artificial intelligence, machine learning, gaming, visual computing, storage and networking.