PCIe 5.0 Simulation Verification Demonstration

PLDA, Aldec and Avery joinly present and demonstrate a new PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA's PCIe 5.0 XpressRICH features include automatic datapath scaling, configurable pipelining (enabling optimal solutions in both ASIC and FPGA), RX Stream mode for custom credit management, L1 PM substrates, dynamically adjustable application clock frequency and clock/power gating.

PLDA® Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect

PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication.

Learn how to configure your PCIe Switch IP

In this video, we will show you just how easy it is  to configure an embedded  PCIe switch with the XpressSWITCH wizard.

 

 

In order to address the increased density of silicon chips and the high performance required by applications in Enterprise Storage and Networking, High performance computing, and AI, SoC designers now have the ability to embed  a PCIe switch instead of employing a traditional external PCIe switch chip.

This enables much reduced latency, power consumption, and complexity, by removing the need for external PHYs.

All PLDA employees remain focused to serve customers and develop leading edge technology

 

100% of PLDA employees in Aix-en-Provence, Hsinchu, San Jose, Shanghai and Sofia are fully operational and are working  remotely. For some activities that sometimes require an absolute presence at the office, such as administration and laboratory tasks, strict rules have been put in place to keep PLDA’s collaborators safe, along with their families and other people from our communities.

Come & meet us at TSMC Symposium/OIP

 

TSMC Symposium / OIP - August 24-25-26
Santa Clara, CA

Come and meet the PLDA Team at TSMC Symposium / OIP North America and TSMC Symposium / OIP Europe!

  • TSMC Symposium/OIP US will take place on august 24/25
  • TSMC Symposium/OIP EUR will take place on august 25/26 

It is an opportunity to learn directly from our experts and discover PLDA's latest High Speed Interconnect solutions, such as:

Come & meet us at Flash Memory Summit 2020

 

Flash Memory Summit - November 10-12

Virtual Conference and Exposition

 

Come and meet the PLDA Team at Flash Memory Summit in Santa Clara!

It is an opportunity to learn directly from our experts and discover PLDA's latest High Speed Interconnect solutions, such as:

Come & meet us at CSIA-ICCAD 2020

 

CSIA-ICCAD - December 10-11

Chongqing Yuelai Internation Center, China

 

Come and meet the PLDA Team at CSIA-ICCAD in China!

It is an opportunity to learn directly from our experts and discover PLDA's latest High Speed Interconnect solutions, such as:

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