PCIe 4.0 Communication over Optical Fiber and TWINAX Cables

As cloud computing and deep learning accelerators drive faster advances in the PCIe roadmap, existing hardware designs cannot support the higher speed signals over the same distances. The PCIe 1.0 specification allowed signals to travel as much as 20 inches over traces in mainstream FR4 boards, even while passing through two connectors. In contrast, today’s quicker 16 GT/s PCIe 4.0 signals will peter out in under six inches and without going over any connectors.

 

 

Gen-Z Primer for Early Adopters

Computer systems as we know them have been built on the paradigm that the CPU-memory pair is fast while network and storage are slow. Over the years, these components developed their own language and interfaces that require layers of software to translate memory commands into network and storage commands and vice versa.

Until now, the speed of the CPU-memory pair relative to network and storage I/O was such that these software layers had minimal impact on system performance.

However, with Moore’s law in full effect, network and storage technologies are quickly catching up with CPU-memory speeds and the burden of generations of software layers now becomes significant.

PLDA and MegaChips announce a cooperation to design PCIe controllers and PCIe PHY IP on TSMC’s 16nm Process Technology

The combination of PLDA’s PCIe controller and MegaChips’ PHY will deliver a complete PCIe subsystem solution.

PLDA, the industry leader in PCI Express® IP solutions and MegaChips, a global semiconductor company specializing in ASIC Solution Services, today announced their collaboration to design a combined PCIe Controller IP and PHY IP solution. While the combination is currently targeting the TSMC 16nm process, the PCIe Controller/PHY solution will be easy to port to additional fabs and processes.

Kazan Networks chooses PLDA PCIe IP

PLDA Announces Integration of their PCIe 3.0 Controller IP into Kazan Networks’ NVMe Over Fabric™ Fuji ASIC, Providing a Dramatic Increase in Scalability and Flexibility for Storage Applications

PLDA and Kazan to Highlight their Products at Flash Memory Summit 2018 in Santa Clara, CA from August 7 – 9, 2018

PLDA and HPE collaborate to develop Gen-Z semiconductor IP

PLDA and HPE collaborate on Gen-Z silicon IP to enable a robust ecosystem of Gen-Z component providers to power memory-driven systems and solutions.

Palo Alto, Calif., July 26, 2018 – Hewlett Packard Enterprise (HPE) and PLDA®, an industry leader in high-speed interconnect IP, today announced a joint collaboration to meet the challenges of next-generation connectivity for advanced workloads. Gen-Z is a new open interconnect protocol and connector developed by the Gen-Z Consortium to solve the challenges associated with processing and analyzing huge amounts of data in real time. HPE and PLDA are working together to develop Gen-Z semiconductor IP designed to the Gen-Z Core Specification 1.0.

PLDA PCIe Experts since 1996

PLDA has been successfully delivering PCI and PCI Express IP for more than 20 years.

With over 6,200 licenses, PLDA has established a vast customer base and the world’s broadest PCIe ecosystem. PLDA has maintained its leadership over four generations of PCI Express specifications, enabling customers to reduce risk and accelerate time to market for their ASIC and FPGA based designs. PLDA provides a complete PCIe solution with its IP cores, FPGA boards for ASIC prototyping, PCIe BFM/testbenches, PCIe drivers, and APIs.

PLDA is a global company with offices in North America (San Jose, California), Europe (France, Italy, and Bulgaria), and Asia (China, Taiwan).

 

 

 

PLDA Announces Availability of XpressRICH5™ PCIe 5.0 Controller IP

PLDA, the industry leader in PCI Express® interface IP solutions, today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP.  PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency. This level of performance is highly anticipated by developers of  leading edge applications in Artificial Intelligence (AI) and Machine Learning (ML), data center storage and networking, and High Performance Computing (HPC).  

PLDA ANNOUNCES XpressCCIX™ CONTROLLER IP SUPPORTING THE CACHE COHERENT INTERFACE FOR ACCELERATORS (CCIX™) STANDARD

PLDA®, the industry leader in PCI Express® interface IP solutions today released its XpressCCIX IP, supporting CCIX™ or Cache Coherent Interconnect for Accelerators (X). The decision to support CCIX is fueled by an increasing demand for higher throughput for PCIe-based systems, driven largely by enterprise and data center customers.

The CCIX Consortium has developed the Cache Coherent Interconnect for Accelerators (X) protocol to enable a new class of interconnect focused on emerging acceleration applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology.

PLDA Solutions for Test and Validation of PCIe 4.0 Devices

In addition to their core business of licensing PCIe semiconductor IP, PLDA has a long history of robust hardware designs. PLDA initially built its first PCIe 4.0 platform, Gen4SWITCH, as a way to demonstrate the PCIe 4.0 technology and to test designs at PCIe 4.0 speed for its own needs. Widely used during tradeshows and at PCI-SIG workshops as an early PCIe 4.0 host platform, Gen4SWITCH has become a star product in high demand, and has spawned a complete Test and Validation product line, targeted specifically at the needs of PCIe 4.0 SoC designers and system vendors.

 

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