PLDA Announces Major PCIe 5.0 Design Win on Cutting Edge 5nm Process Node

 

PLDA, the industry leader in PCI Express® IP and interconnect solutions, today announced a major PCIe 5.0 design win on cutting edge 5nm process node. PLDA’s PCIe 5.0 Controller IP was selected not only for its solid design and unmatched compatibility with popular PCIe PHYs, but also for PLDA’s best-in-class tech support, its ease of customization and PLDA’s integration expertise.

PLDA Reaches Key Milestone in Gen-Z IP Development

In support of immediate Gen-Z development, PLDA has released a detailed datasheet enabling designers to begin architecting and designing Gen-Z enabled SoCs. This PLDA Gen-Z IP datasheet includes the key information required for initial design including supporting features, interface description and micro architecture, gate count, performance metrics, and more.

Enabling Composable Platforms with On-Chip PCIe Switching, PCIe-over-Cable

1. Introduction

Modern enterprise workloads in AI and data analytics are driving the need for new compute and storage architectures in IT infrastructures. The growing use of accelerators (GPUs, FPGAs, custom ASICs) and emerging memory technologies (3D XPoint, Storage Class Memory, Persistent Memory), and the need to better distribute and utilize these resources are fueling the transition to composable/disaggregated infrastructures (CDI) in data centers.

PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow’s SoCs?

1. Introduction

Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.

In this article, we look into the various protocols by providing a brief history, a quick technical comparison, and the latest deployment status. We also offer our perspective on the evolution of these protocols.

Video description of vDMA-AXI IP

The explosion in data traffic due to the advent of Artificial Intelligence, machine learning, automotive and IoT prompts for new System-on-Chip architectures that allow system developers to build high-performance applications that are able to ingest and process huge amounts of heterogeneous data.

 

 

Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms

1. Introduction

As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc.

The transition to PCIe 4.0 and 5.0 with increasing PCIe signaling speeds (16GT/s and 32GT/s) also augments the risk of errors due to tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g. crosstalk, line attenuation, jitter, etc.).

Brite Semiconductor, Naneng Microelectronics, and PLDA Collaborate to Release Complete PCIe 2.0/3.0 Solution

Shanghai, China—Dec 11, 2018

Brite Semiconductor (“Brite”), a world-leading ASIC design service and DDR controller/PHY IP provider headquartered in Shanghai, China, today announced their collaboration with Naneng Microelectronics and PLDA to deliver a complete PCIe 2.0/3.0 solution based on SMIC’s 40nm and 55nm process technology.

Guosheng Wu, CEO of Naneng Microelectronics, said, “Collaboration between Naneng and Brite can effectively reduce the risks and costs of SoC design by providing a low power consumption and small-area PCIe-2.0/3.0 solution based on SMIC’s 40nm and 55nm process, that meets the latest PIPE specifications and supports 2.5G and 5G data rate. We are looking forward to working with Brite to provide customers with a global solution that offers high performance and low cost, while complying with the relevant standards.”

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