PLDA CTO speaks: Enabling next-generation SoC on Samsung advanced process nodes with PCIe 5.0/6.0 and CXL IP

 

Enabling next-generation SoC on Samsung advanced process nodes with PCIe 5.0/6.0 and CXL integrated PHY+Controller IP

Exponential data growth is driving the need for increased performance in Enterprise and Data Center applications, and resulted in the emergence of new interconnect technologies such as CXL and CCIX, and faster transition to PCIe 5.0 and PCIe 6.0. This presentation looks at the different protocol technologies and introduces PLDA and Alphawave joint Controller and PHY IP solution for the Samsung Advanced Process Nodes.  

We describe the joint solution in terms of features and capabilities, and present the stringent verification and validation methodology in place to guarantee first-pass silicon success for Samsung Foundry customers.
 

Tags: PCIe 5.0
Event date: Friday, November 6, 2020

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