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PCIe® 5.0 Link Training at 32 GT/s between PLDA's PCIe 5.0 controller and Broadcom PHY
The demonstration reaffirms the reliability and flexibility of the combined solution for SoC designers
PLDA, the industry leader in PCI Express® controller IP solutions has today unveiled their PCIe 5.0 demonstration. The demo showcases stable PCIe 5.0 Link Training (32 GT/s) and exceptional signal integrity with a Broadcom® PCIe 5.0 PHY platform.
PCIe 5.0 Simulation Verification Demonstration
PLDA, Aldec and Avery joinly present and demonstrate a new PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA's PCIe 5.0 XpressRICH features include automatic datapath scaling, configurable pipelining (enabling optimal solutions in both ASIC and FPGA), RX Stream mode for custom credit management, L1 PM substrates, dynamically adjustable application clock frequency and clock/power gating.
Learn how to configure your PCIe Switch IP
In this video, we will show you just how easy it is to configure an embedded PCIe switch with the XpressSWITCH wizard.
In order to address the increased density of silicon chips and the high performance required by applications in Enterprise Storage and Networking, High performance computing, and AI, SoC designers now have the ability to embed a PCIe switch instead of employing a traditional external PCIe switch chip.
This enables much reduced latency, power consumption, and complexity, by removing the need for external PHYs.
Learn how to configure a PCIe IP with an AXI interconnect
In this video, we walk through the PLDA XpressRICH-AXI™ IP wizard.
PLDA XpressRICH-AXI Controller IP is the #1 choice for ASIC, SoC and FPGA designers looking for an enterprise-class PCIe interface solution with a high-performance, reliable, and scalable AMBA 3 AXI/AMBA 4 AXI interconnect.
Video: Discover how to configure XpressRICH IP
In this video, we talk about the PLDA XpressRICH IP wizard which has been designed to enable PCIe designers to easily configure their PCIe controller as required for their application.
How to debug a PCIe device when it is not detected by the system
PCIe Device links as expected (L0 in x8-Gen4) but is not detected by the system
How Inspector accelerate your hardware validation cycle
Discover how Inspector can be used all along your hardware validation cycle
Virtualized PCIe with Many-Channel DMA Throughput Demo
In this video, we show how SoC designers can leverage the vDMA engine built into PLDA’s XpressRICH-AXI PCIe controller to manage concurrent high performance data traffic between a virtualized PCIe device and multiple Virtual Machines running on the host platform.
Video description of vDMA-AXI IP
The explosion in data traffic due to the advent of Artificial Intelligence, machine learning, automotive and IoT prompts for new System-on-Chip architectures that allow system developers to build high-performance applications that are able to ingest and process huge amounts of heterogeneous data.