Technical Article

Certain applications and hardware types -- emerging memory, artificial intelligence/machine learning, and cloud servers, to name a few -- can realize significant performance advantages when a low latency interface is employed. The CXL (Compute Express Link™) standard was developed specifically as a low latency offshoot of the ever-popular PCIeTM (PCI ExpressTM), and is finding its footing in many of the applications listed.

Let’s compare typical latency of existing standards first. Data shown below is gathered from a variety of industry sources: 

In our last article, we address some of the changes in the PCIe 6.0 specification versus prior generations. Of note in that was that the release cadence of specifications has greatly increased.

As a reminder of how the PCIe specification has evolved:

Figure 1: PCIe Evolution

Looking at the table above, you can see that pre-4.0, specifications were updated every 4.6 years on average. However, since 4.0, the cadence has greatly increased, with a release every 2 years. A logical question here might be ‘why have 5.0 and 6.0 come so fast?’

Today, PLDA announced our PCIe 6.0 controller IP. This announcement builds on PLDA’s track record of being the high speed interface IP provider of choice.

As PCIe 6.0 is quite new, let’s run through a bit about how it differs from previous generations, and why this should matter to a system designer or chip architect as they consider their next generation designs.

While the PCIe 6.0 specification is expected to be finalized and released later in 2021 (Fig 2), PLDA has been hard at work to address the needs of early adopters looking for the most advanced PCIe 6.0 IP solution for their SoCs and ASICs.

There are significant advances in communication protocols happening all around us. The Peripheral Component Interconnect Express (PCIe) Gen 5 standard is delivering the needed device-to-device performance to support artificial intelligence and machine learning applications as well as cloud-based workloads. The rapidly evolving Compute Express Link (CXL) standard is delivering CPU-to-device and CPU-to-memory communication to enable next-generation data center performance. Both are critical enablers for next generation systems and require support in the form of semiconductor IP to be deployed. PLDA has made recent announcements regarding significant milestones for both PCIe and CXL, which is not a common occurrence. I wanted to look a bit closer at both of these announcements to see how PLDA is at the leading edge with advances in both PCIe 5.0 and CXL.

A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™.  The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum link rate of 32GT/s per lane. There are a lot of parts to this specification and multiple implementation options, so a comprehensive support package will significantly help adoption. This is why PLDA brings flexible support for compute express link (CXL) to SoC and FPGA designers.

The Options

The three previously mentioned protocols that make up CXL are:

We recently published a Webinar about the benefits of CXL to reduce latency. After exploring the following topics:

PLDA’s INSPECTOR diagnostic and debug tool for PCIe 4.0 ​that successfully passed the PCIe 4.0 PCI-SIG compliance has two new major features:

• Analog monitoring: The Inspector V2.2 allows now to measure in live the DUT power consumption (3.3V / 12V) and the Inspector temperature. These indications are displayed using dynamic and easily readable charts. This can help SDDs vendors to quickly characterize the impact of PCI-Express low power modes or high throughputs for example.

1. Introduction

Modern enterprise workloads in AI and data analytics are driving the need for new compute and storage architectures in IT infrastructures. The growing use of accelerators (GPUs, FPGAs, custom ASICs) and emerging memory technologies (3D XPoint, Storage Class Memory, Persistent Memory), and the need to better distribute and utilize these resources are fueling the transition to composable/disaggregated infrastructures (CDI) in data centers.

1. Introduction

Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.

In this article, we look into the various protocols by providing a brief history, a quick technical comparison, and the latest deployment status. We also offer our perspective on the evolution of these protocols.