PLDA, the industry leader in high-speed interconnect solutions, today announced their CXL™ Verification IP Ecosystem which includes IP from partners Truechip and Avery Design Systems, who are pioneering CXL design verification. Compute Express Link™ (CXL) is an open industry standard interconnect that builds on PCI Express 5.0’s infrastructure to reduce complexity and system cost while increasing performance. PLDA’s CXL Verification IP Ecosystem is intended to reduce the challenges of designing new CXL applications. By combining leading third-party VIP and PLDA’s best-in-class CXL controller IP, CXL designers will have the ability to choose the most flexible and complete solution for their SoC designs, eliminating reliance on single-source suppliers – an essential step to reducing design risk.
CXL is an emerging interface that leverages PCIe 5.0 architecture for the CXL.io path and adds CXL.cache and CXL.mem paths specific to CXL. This combination presents possible risks for early adopters since a CXL device will be required to pass PCIe 5.0 compliance and also verify CXL specific functionality such as CXL L2 Rules, CXL EDS, CXL Retry, CXL Block Align Error and others. With no hardware available for interoperability validation, the design burden increasingly relies on verification tools to ensure that the simulation and verification steps are solid and reliable.
PLDA’s CXL Verification IP Ecosystem addresses this challenge by enabling several pre-integrated testbenches designed by Avery Design System and Truechip with their respective VIPs and testsuites. The verification ecosystem provides in-depth verification of a complete solution with feature-aligned IP and VIPs for CXL 2.0 and the PCIe 5.0 specifications. Pre-integrated testbenches are already available to customers. They can by now initiate their evaluation, and greatly speed-up the early verification stages of their IP integration.
According to Chris Browy, vice president of sales/marketing at Avery, “We are excited to collaborate with PLDA to create a best-in-class, robust, pre-validated CXL 2.0 IP solution that streamlines the design and verification process and fosters the rapid adoption of the CXL standard. PLDA and Avery are long-term partners and are both respected leaders in Design IP and VIP and work closely to enable achieving the highest quality CXL IP solutions.” Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe 5.0 and CXL 2.0/1.1 for CXL host, Type 1-3 devices, switches, and retimers.
On this occasion, Nitin Kishore, CEO, Truechip, said, “Our collaboration with PLDA emphasizes our shared values of creativity, technological innovation and robust solutions like CXL 2.0. CXL is a cache coherent interconnect which aims to remove bottlenecks between CPU and high bandwidth devices or memory subsystems. CXL’s applications include Artificial Intelligence, Machine Learning and next generation data centers”. He further added “Given the complexity, it requires careful implementation and comprehensive testing and our partnership with PLDA augments customers to experience the verified IPs. Truechip’s Verification IP solutions are of choice as we are known in the industry for aggressive and dedicated support, customization, flexibility and TruEye™ GUI for easy debugging.”
According to Stephane Hauradou, CTO of PLDA “CXL is an important evolutionary step in interface design because of its inherent latency and performance advantages, however ensuring reliable and robust verification is critical to its adoption. The PLDA CXL Verification IP Ecosystem is an important advancement in this direction”
For more information on CXL products and to access the PLDA CXL 1.1/2.0 Verification IP Ecosystem: