Using the same silicon-proven IP found in PLDA’s XpressRICH3 product, PLDA’s PCIe 4.0 controller IP and Bus Functional Model (BFM) enable SoC and ASIC designers to quickly incorporate PCIe 4.0. PLDA provides testing and integration with third party PHYs, delivering a complete and flexible PCIe 4.0 solution.
PCIe 4.0 is the next evolution of the widely implemented PCI Express I/O specification. At 16Gbps, the interconnect performance bandwidth will be doubled over the current PCIe 3.0 specification, while preserving compatibility with software and mechanical interfaces.
PLDA PCIe 4.0 Benefits
- Proven XpressRICH3 architecture is preserved to enable easy migration to PCIe 4.0
- No interface change is necessary, existing behavior is preserved for seamless integration.
- Variety of Supported PIPE Configurations for PCIe 4.0: PIPE 16-bit is supported in x1, x2, x4, x8 and x16 with 500MHz PIPE clock at 8Gbps (ASIC)
- PIPE 32-bit is supported in x1, x2, x4, x8 with 500MHz PIPE clock at 16Gbps (ASIC)
- PIPE 64-bit will be supported in x1, x2 and x4 with 250MHz PIPE clock at 16Gbps (ASIC/FPGA)
- PLDA PCIe Controller IP currently uses PIE-8 specification, enabling easy integration with PCS layer from multiple PHY vendors
- PLDA actively participates in PIE-8 2.0 specification update which will support 16Gbps
PHY Interoperability and Partnerships
- PLDA will provide a fully integrated “Controller + PHY” solution for PCIe 4.0 targeting various Foundry/Process combinations.
- PLDA’s PHY Interoperability Test Suite for PCIe 4.0 is available to customers and partners (PHY vendors and ASIC vendors)
- PLDA is currently partnering with major PHY vendors to have an integrated PHY/Controller solution. Visit PLDA Partner Ecosystem