With the draft specification available and the upcoming release of the final PCIe Gen 6 specification, system designers are beginning to plan how to build the specification’s new features into their products.
In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.
You Will Learn:
- Design considerations for PCIe 6
- Challenges unique to verifying PCIe 6 designs
- Designing workflow and testbench requirements for PCIe 6
- Tips and tricks for debugging PCIe 6
Who Should Attend:
- Design & Verification Engineers & Managers and those developing complex testbenches for SoC Verification using standard Verification IP components including PCIe 6