DAC 2018: San Francisco, CA - June 24-28
WEDNESDAY June 27, 10:30am - 12:00pm - Room 2008
LATEST DEVELOPMENTS IN HIGH PERFORMANCE SOC INTERFACE IP STANDARDS
We live in the world where there are overlapping interface IP standards, and SOC architects face challenge of making critical decision on right interface adoption. The interface IP standards constantly evolve, and there is industry push to develop new standards to address gaps. Studying latest developments in Interface IP standards is very critical to successful product definition. This session focuses on introducing an upcoming interface technology standard, and key challenges it addresses. The session also focuses on bringing in latest developments in some of the key interface standards, upcoming trends, key application areas, and IP providers. This will help architects and product managers decide on right standard adoption for their products, and educate designers on newer developments.
WILL PCIE 5.0 BECOME UBIQUITOUS IN TOMORROW'S SoCs?
Speaker: Trupti Gowda - PLDA
The race to gain silicon market share in the Enterprise space prompts semiconductor companies to develop SoCs with communication interfaces that provide the highest performance while enjoying broad market adoption. In this presentation we look at the PCIe 5.0 specification and its positioning in the boiling market of high speed interfaces. We review the challenges and pitfalls associated with the implementation of the PCIe5.0 interface protocol and provide some guidelines for successful integration in SoCs.