Today, PLDA announced our PCIe 6.0 controller IP. This announcement builds on PLDA’s track record of being the high speed interface IP provider of choice.
As PCIe 6.0 is quite new, let’s run through a bit about how it differs from previous generations, and why this should matter to a system designer or chip architect as they consider their next generation designs.
Over the course of two decades, PCI Express® (PCIe®) has become the de-facto I/O interconnect in electronic systems, by providing the level of performance and reliability expected by cloud, enterprise, consumer, industrial, and automotive applications.
As the need for data has exploded driven by applications like AI/ML and automotive, the semiconductor industry, led by PCI-SIG, is preparing for the final release of the PCIe 6.0 specification and all the changes it entails.
In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.
What you will learn:
- what is PCIE 6.0
- how does it differ from past generations
- design considerations when planning with PCIe 6
- verification implications of a PCIe 6 design
Highlights:
