• Building Start Scalable Storage SoCs with Embedded PCIe Switching (Chinese)

    As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architects to look for ways to differentiate and future-proof their designs.
    In this presentation we look at current storage architectures and propose an innovative way to design next-generation storage SoCs centered around the use of embedded PCIe switching.
    We then introduce PLDA’s PCIe switch IP along with some real-world use cases, and explore the various IP features and capabilities that enable differentiation and future-proofing of SoCs in storage applications and beyond.

  • PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers

    A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™.  The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum link rate of 32GT/s per lane. There are a lot of parts to this specification and multiple implementation options, so a comprehensive support package will significantly help adoption. This is why PLDA brings flexible support for compute express link (CXL) to SoC and FPGA designers.

    The Options

    The three previously mentioned protocols that make up CXL are:

  • PLDA Announces the Successful CXL™ Interoperability with pre-production Intel Xeon CPU, Code Named Sapphire Rapids

    PLDA XpressLINK™ CXL Controller IP combines the industry’s lowest latency implementation with an easy-to-integrate design, accelerating adoption of CXL in SoC designs.

     

    PLDA, the industry leader in high-speed interconnect solutions, today announced the successful CXL™ interoperability with pre-production Intel Xeon processors code named Sapphire Rapids. The session was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. It resulted in demonstrated interoperability between PLDA’s XpressLINK™ CXL IP, running on a PLDA FPGA-based add-in card, and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors.