Senior Design Engineer

Aix-en-Provence, France - Full-time

About PLDA

PLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, CXL, and Gen-Z. PLDA has established itself as a leader in that space with over 3,200 customers and 6,400 licenses in 62 countries. PLDA is a global technology company with offices in Silicon Valley, France, Bulgaria, Taiwan, and China.

Your Mission

  • Define the micro-architecture and implement the RTL design of IP blocks that comply with the given specifications and requirements
  • Ensure the designs meet quality, performance, schedule, and cost goals
  • Collaborate and communicate with management regarding design status, project progress and issue resolution
  • Provide customer level 3 technical support for the implemented design

Skills Requirement

  • Verilog or VHDL RTL Design

Additional Desirable Skills

  • ASIC and FPGA design flow
  • High performance computing system, processor, cache coherency, chipset and ASICs
  • High speed interface protocols like PCIe, CCIX, CXL, Gen-Z, others
  • High performance memory interfaces
  • Knowledge on High Speed Serdes and PHY PMA
  • Proficiency in programming and/or scripting languages (Python, Cshell…)

Your Profile

  • 10+ years of experience
  • Good English skills, communication skills, and willingness to work with an international team