PLDA Announces Live PCI Express Gen3 x8 Demo Running on Xilinx Kintex-7 FPGA

PLDA, the industry leader in PCI Express® and high-speed interface IP, today announced it will be debuting a live PCIe® x8 Gen3 demo featuring PLDA’s leading PCIe Gen3 soft IP core and running on a Xilinx Kintex-7 FPGA during the DAC Conference, June 3 -7 in San Francisco, CA. The PLDA PCIe Gen3 IP core is the first to run on a -2 medium speed grade Xilinx Kintex-7 FPGA while consuming only a fraction of available device resources, allowing unmatched design flexibility.

“PLDA has become known as a go-to partner for PCIe and reliable high-speed interface IP solutions, consistently pushing the design envelope for our customers”.

Integration of PLDA's PCIe 2.0 controller with advanced AMBA(R) AXI interface in Microsemi's new SmartFusion2 SoC FPGA

PLDA, the industry leader in PCI Express(R) and high-speed interface IP today announced incorporation of its PCIe-AXI bridge IP into Microsemi Corporation's recently announced SmartFusion(R)2 SoC FPGA. Microsemi's SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in a wide range of critical applications. SmartFusion2 integrates an inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM(R) Cortex(TM)-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM, and industry-required high-performance communication interfaces all on a single chip.

First Successful PCIe Gen 3 Controller and PHY Combination on TSMC’s 28nm

PLDA, the industry leader in PCI Express® IP solutions and GUC, the Flexible ASIC LeaderTM , today announced successful test chips for the industry’s first combined PCIe Gen 3 Controller IP and PHY IP solution on TSMC 28nm HPM (High Performance Mobile) process. The combined PCIe 3.0 Controller/PHY solution is in initial production and has been incorporated into demo boards.

 

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