Anritsu Corporation Selects PLDA’s PCIe Solution for its Next Generation of Handheld Spectrum Analyzers

PLDA, the industry leader in high-speed interconnect, today announced that Anritsu Corporation has selected PLDA’s PCIe Controller IP for its next generation of handheld spectrum analyzers. Anritsu, a global provider of innovative communications test and measurement solutions, joins a growing number of companies worldwide implementing PLDA solutions.

PCIe Technology has long been used by the test and measurement Industry, as high-quality and configurable PCIe IPs are perfectly optimized for high-end analyzers. The maturity of PLDA’s PCIe controller solution on ASIC and FPGA technologies and the company’s reputation for outstanding customer support were among the key deciding factors for Anritsu. 

PLDA Introduces a Complete Line of PCIe® IP for USB4®, Enabling PCIe Support in USB4 Hubs, Hosts and Devices

PLDA, the leading developer of high-speed interconnect silicon IP, today announced the launch of a new, complete line of PCIe Controller IP products specifically tailored for use in USB4 ICs. PLDA’s PCIe product line for USB4 allows designers to implement internal PCIe devices in their USB4 ASIC designs, resulting in reduced latency and power consumption. This provides a step forward in design methodology for applications including:

PLDA Joins ETP4HPC to share its expertise in High Speed Interconnect Solution IP with the European High Performance Computing Ecosystem

 

PLDA, the leading developer of high-speed interconnect silicon IP, is joining ETP4HPC, an association that gathers leading European players in high performance computing technologies.

ETP4HPC – the European Technology Platform (ETP) for High-Performance Computing (HPC) - is a private, industry-led and non-profit association whose main mission is to promote European HPC research and innovation in order to maximise the economic and societal benefits of HPC for European science, industry, and citizens.

Alphawave and PLDA Announce a Collaboration to Create Tightly-Integrated Controller and PHY IP Solutions for Interconnects Including PCIe® 5.0, CXL™ and PCIe 6.0

PLDA, the industry leader in high-speed interconnect solutions, and Alphawave, a leading provider of multi-standard connectivity IP solutions for electronic devices, today announced a collaboration designed to provide the industry’s most robust IP solutions for interconnect technologies most commonly used today such as PCIe® 5.0 and CXL™. They will also begin collaborating on future technologies including PCIe 6.0. 

PLDA Announces a Unique CXL™ Verification IP Ecosystem, Delivering Robust Verification That Reduces Time-to-Design for CXL 2.0 Applications

PLDA, the industry leader in high-speed interconnect solutions, today announced their CXL™ Verification IP Ecosystem which includes IP from partners Truechip and Avery Design Systems, who are pioneering CXL design verification. Compute Express Link™ (CXL) is an open industry standard interconnect that builds on PCI Express 5.0’s infrastructure to reduce complexity and system cost while increasing performance. PLDA’s CXL Verification IP Ecosystem is intended to reduce the challenges of designing new CXL applications. By combining leading third-party VIP and PLDA’s best-in-class CXL controller IP, CXL designers will have the ability to choose the most flexible and complete solution for their SoC designs, eliminating reliance on single-source suppliers – an essential step to reducing design risk. 

PLDA Announces XpressLINK-SOC™ CXL Controller IP with Support for the AMBA CXS Issue B Protocol

PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDA’s industry-leading XpressLINK-SOC™ CXL IP provides full support for the AMBA® CXS Issue B (CXS-B) interface protocol. This support enables SoC designers to reduce latency and more easily implement the CXL and CCIX multichip interconnect standards in their Arm®-based System-on Chip (SoC) solutions.

AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller. Using a CXS interface, the designer can bypass the controller’s transaction layer, which can significantly reduce latency. The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink™ Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets. 

PLDA is at the Leading Edge with Advances in Both PCIe 5.0 and CXL

There are significant advances in communication protocols happening all around us. The Peripheral Component Interconnect Express (PCIe) Gen 5 standard is delivering the needed device-to-device performance to support artificial intelligence and machine learning applications as well as cloud-based workloads. The rapidly evolving Compute Express Link (CXL) standard is delivering CPU-to-device and CPU-to-memory communication to enable next-generation data center performance. Both are critical enablers for next generation systems and require support in the form of semiconductor IP to be deployed. PLDA has made recent announcements regarding significant milestones for both PCIe and CXL, which is not a common occurrence. I wanted to look a bit closer at both of these announcements to see how PLDA is at the leading edge with advances in both PCIe 5.0 and CXL.

PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers

A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™.  The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum link rate of 32GT/s per lane. There are a lot of parts to this specification and multiple implementation options, so a comprehensive support package will significantly help adoption. This is why PLDA brings flexible support for compute express link (CXL) to SoC and FPGA designers.

The Options

The three previously mentioned protocols that make up CXL are:

PLDA Announces the Successful CXL™ Interoperability with pre-production Intel Xeon CPU, Code Named Sapphire Rapids

PLDA XpressLINK™ CXL Controller IP combines the industry’s lowest latency implementation with an easy-to-integrate design, accelerating adoption of CXL in SoC designs.

 

PLDA, the industry leader in high-speed interconnect solutions, today announced the successful CXL™ interoperability with pre-production Intel Xeon processors code named Sapphire Rapids. The session was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. It resulted in demonstrated interoperability between PLDA’s XpressLINK™ CXL IP, running on a PLDA FPGA-based add-in card, and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors.

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