XpressSWITCH™ IP First Ever Switch Soft IP to pass PCI-SIG PCIe 4.0 Compliance Tests
PLDA XpressSWITCH IP passed all Gold and Interoperability tests as a Switch Component at PCIe 4.0 architecture speed (16 GT/s)
XpressSWITCH™ IP is the Industry’s first switch Soft IP (SIP) to pass all Gold and Interoperability tests at the PCI-SIG® Compliance Workshop 115, held online in October 2020. The testing was conducted using PLDA XpressSWITCH IP for the PCI Express® (PCIe®) 4.0 specification, running on a FPGA based add-in card with both upstream and downstream ports operating at 16 GT/s.
PCIe® 5.0 Link Training at 32 GT/s between PLDA's PCIe 5.0 controller and Broadcom PHY
The demonstration reaffirms the reliability and flexibility of the combined solution for SoC designers
PLDA, the industry leader in PCI Express® controller IP solutions has today unveiled their PCIe 5.0 demonstration. The demo showcases stable PCIe 5.0 Link Training (32 GT/s) and exceptional signal integrity with a Broadcom® PCIe 5.0 PHY platform.
CXL Webinar: Q/A session

We recently published a Webinar about the benefits of CXL to reduce latency. After exploring the following topics:
PCIe 5.0 Simulation Verification Demonstration
PLDA, Aldec and Avery joinly present and demonstrate a new PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA's PCIe 5.0 XpressRICH features include automatic datapath scaling, configurable pipelining (enabling optimal solutions in both ASIC and FPGA), RX Stream mode for custom credit management, L1 PM substrates, dynamically adjustable application clock frequency and clock/power gating.
PLDA® Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect
PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication.
Learn how to configure your PCIe Switch IP
In this video, we will show you just how easy it is to configure an embedded PCIe switch with the XpressSWITCH wizard.
In order to address the increased density of silicon chips and the high performance required by applications in Enterprise Storage and Networking, High performance computing, and AI, SoC designers now have the ability to embed a PCIe switch instead of employing a traditional external PCIe switch chip.
This enables much reduced latency, power consumption, and complexity, by removing the need for external PHYs.
PLDA Announce Complete Support for CXL™ and Gen-Z™ protocols
Following the recent Announcement of MoU between the CXL Consortium™ and the Gen-Z Consortium™, PLDA Launches their XpressLINK™ CXL IP, providing an immediate Compute Express Link solution for SoC developers
All PLDA employees remain focused to serve customers and develop leading edge technology
100% of PLDA employees in Aix-en-Provence, Hsinchu, San Jose, Shanghai and Sofia are fully operational and are working remotely. For some activities that sometimes require an absolute presence at the office, such as administration and laboratory tasks, strict rules have been put in place to keep PLDA’s collaborators safe, along with their families and other people from our communities.
Learn how to configure a PCIe IP with an AXI interconnect
In this video, we walk through the PLDA XpressRICH-AXI™ IP wizard.
PLDA XpressRICH-AXI Controller IP is the #1 choice for ASIC, SoC and FPGA designers looking for an enterprise-class PCIe interface solution with a high-performance, reliable, and scalable AMBA 3 AXI/AMBA 4 AXI interconnect.