Enabling Composable Platforms with On-Chip PCIe Switching, PCIe-over-Cable

1. Introduction

Modern enterprise workloads in AI and data analytics are driving the need for new compute and storage architectures in IT infrastructures. The growing use of accelerators (GPUs, FPGAs, custom ASICs) and emerging memory technologies (3D XPoint, Storage Class Memory, Persistent Memory), and the need to better distribute and utilize these resources are fueling the transition to composable/disaggregated infrastructures (CDI) in data centers.

PCIe Switch IP Presentation and Demo

 

PLDA Switch IP for PCIe is a customizable and scalable switch design intended to be embedded into ASIC, SoC, and FPGA. PCIe® architecture has become a standard in the enterprise space due to the advantages it provides in term of performance and reliability. Embedding a configurable PCIe switch IP into chip designs provides developers with extra flexibility, scalability and reliability when interconnecting multiple PCIe devices, with significant gains in term of latency and power consumption compared to ASSP solutions.