Webinar: Verification of PCIe® 6.0 IP

 

With the draft specification available and the upcoming release of the final PCIe Gen 6 specification, system designers are beginning to plan how to build the specification’s new features into their products.

In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.

Why PCIe 6.0 Now?

In our last article, we address some of the changes in the PCIe 6.0 specification versus prior generations. Of note in that was that the release cadence of specifications has greatly increased.

As a reminder of how the PCIe specification has evolved:

Figure 1: PCIe Evolution

 

Looking at the table above, you can see that pre-4.0, specifications were updated every 4.6 years on average. However, since 4.0, the cadence has greatly increased, with a release every 2 years. A logical question here might be ‘why have 5.0 and 6.0 come so fast?’

On PCIe 6.0

Today, PLDA announced our PCIe 6.0 controller IP. This announcement builds on PLDA’s track record of being the high speed interface IP provider of choice.

As PCIe 6.0 is quite new, let’s run through a bit about how it differs from previous generations, and why this should matter to a system designer or chip architect as they consider their next generation designs.