PCIe 5.0 Simulation Verification Demonstration

PLDA, Aldec and Avery joinly present and demonstrate a new PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA's PCIe 5.0 XpressRICH features include automatic datapath scaling, configurable pipelining (enabling optimal solutions in both ASIC and FPGA), RX Stream mode for custom credit management, L1 PM substrates, dynamically adjustable application clock frequency and clock/power gating.

PLDA® Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect

PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication.