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PLDA’s strong Ecosystem and stringent 4-step integration process delivers pre-integrated and well-tested PCIe Controller and PHY solutions, solving many of the challenges and concerns faced by SoC designers
PLDA to Showcase its Extensive PCIe Ecosystem During DAC 2016
ASIC Designers and Project Managers can explore the industry’s best suite of tested, silicon-proven, third-party PCIe solutions in one place.
SAN JOSE, Calif., June 6, 2016 -- PLDA, the industry leader in PCI Express® interface IP solutions today announced a focus on their extensive PLDA Ecosystem Partners at their booth during the DAC 2016 show to be held June 6 – 8, 2016 in Austin, Texas. In addition to showcasing their broad selection of PCIe and interface IP, PLDA is providing information on how ASIC designers can accelerate their time-to-market through easy-to-integrate and tested PCIe solutions using the PLDA Ecosystem.
PLDA and GUC Delivers Fully Integrated PCI Express Gen 4 Solution for TSMC’s 16nm FinFET Plus Process
PCIe 4.0 Controller and PHY Provide Complete IP Solution Enabling Early Adopters of the Emerging PCIe 4.0 Specification to Accelerate Product Development and Reduce Integration Risk. See a demonstration at The TSMC Symposium in San Jose on April 7th.
PLDA and GUC Announce a tested and reliable PCIe Controller and PHY combination, optimized for storage applications
PLDA XpressRICH3 PCIe controller and GUC PCIe PHY combo delivers a high performance, integrated solution, optimizing time-to-market
SAN JOSE, Calif. (June 9, 2014) — PLDA, the industry leader in PCI Express® IP solutions and GUC, the Flexible ASIC LeaderTM , today announced a combined PCIe Gen 3 Controller IP and PHY IP solution, optimized for the needs of the storage market. The combined PCIe 3.0 Controller/PHY solution is in initial production and has been incorporated into a demo board.
First Successful PCIe Gen 3 Controller and PHY Combination on TSMC’s 28nm
PLDA, the industry leader in PCI Express® IP solutions and GUC, the Flexible ASIC LeaderTM , today announced successful test chips for the industry’s first combined PCIe Gen 3 Controller IP and PHY IP solution on TSMC 28nm HPM (High Performance Mobile) process. The combined PCIe 3.0 Controller/PHY solution is in initial production and has been incorporated into demo boards.