PCIe 4.0 Communication over Optical Fiber and TWINAX Cables

As cloud computing and deep learning accelerators drive faster advances in the PCIe roadmap, existing hardware designs cannot support the higher speed signals over the same distances. The PCIe 1.0 specification allowed signals to travel as much as 20 inches over traces in mainstream FR4 boards, even while passing through two connectors. In contrast, today’s quicker 16 GT/s PCIe 4.0 signals will peter out in under six inches and without going over any connectors.

 

 

PLDA Solutions for Test and Validation of PCIe 4.0 Devices

In addition to their core business of licensing PCIe semiconductor IP, PLDA has a long history of robust hardware designs. PLDA initially built its first PCIe 4.0 platform, Gen4SWITCH, as a way to demonstrate the PCIe 4.0 technology and to test designs at PCIe 4.0 speed for its own needs. Widely used during tradeshows and at PCI-SIG workshops as an early PCIe 4.0 host platform, Gen4SWITCH has become a star product in high demand, and has spawned a complete Test and Validation product line, targeted specifically at the needs of PCIe 4.0 SoC designers and system vendors.

 

PLDA, the industry leader in PCI Express® interface IP solutions today announces a demonstration of the industry’s first development platform for PCIe® 4.0

SAN JOSE, Calif., June 28, 2016 -- PLDA, the industry leader in PCI Express® interface IP solutions today announces a demonstration of the industry’s first development platform for PCIe® 4.0. This exclusive demonstration can be viewed in PLDA’s booth at PCI-SIG DevCon, being held in Santa Clara, California on June 28-29, 2016.

PCIe Switch IP Presentation and Demo

 

PLDA Switch IP for PCIe is a customizable and scalable switch design intended to be embedded into ASIC, SoC, and FPGA. PCIe® architecture has become a standard in the enterprise space due to the advantages it provides in term of performance and reliability. Embedding a configurable PCIe switch IP into chip designs provides developers with extra flexibility, scalability and reliability when interconnecting multiple PCIe devices, with significant gains in term of latency and power consumption compared to ASSP solutions.