In support of immediate Gen-Z development, PLDA has released a detailed datasheet enabling designers to begin architecting and designing Gen-Z enabled SoCs. This PLDA Gen-Z IP datasheet includes the key information required for initial design including supporting features, interface description and micro architecture, gate count, performance metrics, and more.
Computer systems as we know them have been built on the paradigm that the CPU-memory pair is fast while network and storage are slow. Over the years, these components developed their own language and interfaces that require layers of software to translate memory commands into network and storage commands and vice versa.
Until now, the speed of the CPU-memory pair relative to network and storage I/O was such that these software layers had minimal impact on system performance.
However, with Moore’s law in full effect, network and storage technologies are quickly catching up with CPU-memory speeds and the burden of generations of software layers now becomes significant.
November 11-16 in Dallas, TX
The Gen-Z Consortium will be showcasing an all-new multi-vendor technology demo at Super Computing 2018 on November 11-16 in Dallas, TX. As an active member of the Gen-Z consortium, PLDA will be part of this booth. Visit the booth #4101 in Hall F to learn more about the applications for Gen-Z technology. More information coming soon!
Learn more about PLDA's Gen-Z IP
PLDA and HPE collaborate on Gen-Z silicon IP to enable a robust ecosystem of Gen-Z component providers to power memory-driven systems and solutions.
Palo Alto, Calif., July 26, 2018 – Hewlett Packard Enterprise (HPE) and PLDA®, an industry leader in high-speed interconnect IP, today announced a joint collaboration to meet the challenges of next-generation connectivity for advanced workloads. Gen-Z is a new open interconnect protocol and connector developed by the Gen-Z Consortium to solve the challenges associated with processing and analyzing huge amounts of data in real time. HPE and PLDA are working together to develop Gen-Z semiconductor IP designed to the Gen-Z Core Specification 1.0.
DAC 2018: San Francisco, CA - June 24-28
WEDNESDAY June 27, 10:30am - 12:00pm - Room 2008
LATEST DEVELOPMENTS IN HIGH PERFORMANCE SOC INTERFACE IP STANDARDS
PLDA ANNOUNCES XpressCCIX™ CONTROLLER IP SUPPORTING THE CACHE COHERENT INTERFACE FOR ACCELERATORS (CCIX™) STANDARD
PLDA®, the industry leader in PCI Express® interface IP solutions today released its XpressCCIX IP, supporting CCIX™ or Cache Coherent Interconnect for Accelerators (X). The decision to support CCIX is fueled by an increasing demand for higher throughput for PCIe-based systems, driven largely by enterprise and data center customers.
The CCIX Consortium has developed the Cache Coherent Interconnect for Accelerators (X) protocol to enable a new class of interconnect focused on emerging acceleration applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology.
PLDA Further Strengthen Partner Ecosystem, Unveils Comprehensive PCIe PHY and Controller integrated Solutions
PLDA’s strong Ecosystem and stringent 4-step integration process delivers pre-integrated and well-tested PCIe Controller and PHY solutions, solving many of the challenges and concerns faced by SoC designers