Demonstration of a CXL Interconnect on a FPGA-based design

 

In this video, we demonstrate the PLDA XpressLINK Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon CPU as a host, connected to an FPGA board, instantiating PLDA’s CXL Controller and CXL.mem test design. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

 

 

 

Reducing CXL Latency with PLDA and AnalogX

 

Certain applications and hardware types -- emerging memory, artificial intelligence/machine learning, and cloud servers, to name a few -- can realize significant performance advantages when a low latency interface is employed. The CXL (Compute Express Link™) standard was developed specifically as a low latency offshoot of the ever-popular PCIeTM (PCI ExpressTM), and is finding its footing in many of the applications listed.

Let’s compare typical latency of existing standards first. Data shown below is gathered from a variety of industry sources: 

Alphawave and PLDA Announce a Collaboration to Create Tightly-Integrated Controller and PHY IP Solutions for Interconnects Including PCIe® 5.0, CXL™ and PCIe 6.0

PLDA, the industry leader in high-speed interconnect solutions, and Alphawave, a leading provider of multi-standard connectivity IP solutions for electronic devices, today announced a collaboration designed to provide the industry’s most robust IP solutions for interconnect technologies most commonly used today such as PCIe® 5.0 and CXL™. They will also begin collaborating on future technologies including PCIe 6.0. 

PLDA Announces a Unique CXL™ Verification IP Ecosystem, Delivering Robust Verification That Reduces Time-to-Design for CXL 2.0 Applications

PLDA, the industry leader in high-speed interconnect solutions, today announced their CXL™ Verification IP Ecosystem which includes IP from partners Truechip and Avery Design Systems, who are pioneering CXL design verification. Compute Express Link™ (CXL) is an open industry standard interconnect that builds on PCI Express 5.0’s infrastructure to reduce complexity and system cost while increasing performance. PLDA’s CXL Verification IP Ecosystem is intended to reduce the challenges of designing new CXL applications. By combining leading third-party VIP and PLDA’s best-in-class CXL controller IP, CXL designers will have the ability to choose the most flexible and complete solution for their SoC designs, eliminating reliance on single-source suppliers – an essential step to reducing design risk. 

PLDA Announces XpressLINK-SOC™ CXL Controller IP with Support for the AMBA CXS Issue B Protocol

PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDA’s industry-leading XpressLINK-SOC™ CXL IP provides full support for the AMBA® CXS Issue B (CXS-B) interface protocol. This support enables SoC designers to reduce latency and more easily implement the CXL and CCIX multichip interconnect standards in their Arm®-based System-on Chip (SoC) solutions.

AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller. Using a CXS interface, the designer can bypass the controller’s transaction layer, which can significantly reduce latency. The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink™ Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets. 

PLDA Announces CXL™ 2.0 Support in their XpressLINK™ Family of CXL Controller IP

PLDA, the industry leader in high-speed Interconnect solutions, today announced CXL 2.0 support for its XpressLINK™ and XpressLINK-SOC™ CXL IP solutions. Compute Express Link™ (CXL) is an open industry interconnect standard that builds on PCI Express® 5.0 infrastructure to enable memory coherency and low latency between processors and accelerators. The CXL 2.0 specification introduces additional functionality including first level switching, memory pooling and sharing, and Hot Plug, which aim to deliver important benefits for hyperconverged datacenter and HPC applications.

PLDA’s long track record of PCIe® innovation and success has given them an edge in CXL development, and their XpressLINK CXL IP is available now for integration into cutting-edge designs. Key features of PLDA XpressLINK CXL IP include: