PLDA announce the 2nd topic of their Webinar Series: "Building Smart Scalable Storage SoC With Embedded PCIe Switching".
We recently published a Webinar about the benefits of CXL to reduce latency. After exploring the following topics:
PLDA® Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect
PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication.
Following the recent Announcement of MoU between the CXL Consortium™ and the Gen-Z Consortium™, PLDA Launches their XpressLINK™ CXL IP, providing an immediate Compute Express Link solution for SoC developers