PLDA, the industry leader in high-speed interconnect solutions, today announced their CXL™ Verification IP Ecosystem which includes IP from partners Truechip and Avery Design Systems, who are pioneering CXL design verification. Compute Express Link™ (CXL) is an open industry standard interconnect that builds on PCI Express 5.0’s infrastructure to reduce complexity and system cost while increasing performance. PLDA’s CXL Verification IP Ecosystem is intended to reduce the challenges of designing new CXL applications. By combining leading third-party VIP and PLDA’s best-in-class CXL controller IP, CXL designers will have the ability to choose the most flexible and complete solution for their SoC designs, eliminating reliance on single-source suppliers – an essential step to reducing design risk.
PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDA’s industry-leading XpressLINK-SOC™ CXL IP provides full support for the AMBA® CXS Issue B (CXS-B) interface protocol. This support enables SoC designers to reduce latency and more easily implement the CXL and CCIX multichip interconnect standards in their Arm®-based System-on Chip (SoC) solutions.
AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller. Using a CXS interface, the designer can bypass the controller’s transaction layer, which can significantly reduce latency. The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink™ Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets.
There are significant advances in communication protocols happening all around us. The Peripheral Component Interconnect Express (PCIe) Gen 5 standard is delivering the needed device-to-device performance to support artificial intelligence and machine learning applications as well as cloud-based workloads. The rapidly evolving Compute Express Link (CXL) standard is delivering CPU-to-device and CPU-to-memory communication to enable next-generation data center performance. Both are critical enablers for next generation systems and require support in the form of semiconductor IP to be deployed. PLDA has made recent announcements regarding significant milestones for both PCIe and CXL, which is not a common occurrence. I wanted to look a bit closer at both of these announcements to see how PLDA is at the leading edge with advances in both PCIe 5.0 and CXL.
A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™. The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum link rate of 32GT/s per lane. There are a lot of parts to this specification and multiple implementation options, so a comprehensive support package will significantly help adoption. This is why PLDA brings flexible support for compute express link (CXL) to SoC and FPGA designers.
The three previously mentioned protocols that make up CXL are:
PLDA Announces the Successful CXL™ Interoperability with pre-production Intel Xeon CPU, Code Named Sapphire Rapids
PLDA XpressLINK™ CXL Controller IP combines the industry’s lowest latency implementation with an easy-to-integrate design, accelerating adoption of CXL in SoC designs.
PLDA, the industry leader in high-speed interconnect solutions, today announced the successful CXL™ interoperability with pre-production Intel Xeon processors code named Sapphire Rapids. The session was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. It resulted in demonstrated interoperability between PLDA’s XpressLINK™ CXL IP, running on a PLDA FPGA-based add-in card, and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors.
PLDA, the industry leader in high-speed Interconnect solutions, today announced CXL 2.0 support for its XpressLINK™ and XpressLINK-SOC™ CXL IP solutions. Compute Express Link™ (CXL) is an open industry interconnect standard that builds on PCI Express® 5.0 infrastructure to enable memory coherency and low latency between processors and accelerators. The CXL 2.0 specification introduces additional functionality including first level switching, memory pooling and sharing, and Hot Plug, which aim to deliver important benefits for hyperconverged datacenter and HPC applications.
PLDA’s long track record of PCIe® innovation and success has given them an edge in CXL development, and their XpressLINK CXL IP is available now for integration into cutting-edge designs. Key features of PLDA XpressLINK CXL IP include:
We recently published a Webinar about the benefits of CXL to reduce latency. After exploring the following topics:
Following the recent Announcement of MoU between the CXL Consortium™ and the Gen-Z Consortium™, PLDA Launches their XpressLINK™ CXL IP, providing an immediate Compute Express Link solution for SoC developers