PLDA to Demonstrate Industry’s First PCIe® 4.0 Switch Platform with Multiple Downstream Ports during PCI-SIG DevCon 2018
DAC 2018: San Francisco, CA - June 24-28
WEDNESDAY June 27, 10:30am - 12:00pm - Room 2008
LATEST DEVELOPMENTS IN HIGH PERFORMANCE SOC INTERFACE IP STANDARDS
PLDA, the industry leader in PCI Express® interface IP solutions, today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP. PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency. This level of performance is highly anticipated by developers of leading edge applications in Artificial Intelligence (AI) and Machine Learning (ML), data center storage and networking, and High Performance Computing (HPC).
PLDA is organizing a free 1-day technical event for designers (Shanghaï - July 3rd) who want to learn about PCIe design and integration in SoCs.
After attending this 1-day event, SoC Designers will be able to:
PLDA ANNOUNCES XpressCCIX™ CONTROLLER IP SUPPORTING THE CACHE COHERENT INTERFACE FOR ACCELERATORS (CCIX™) STANDARD
PLDA®, the industry leader in PCI Express® interface IP solutions today released its XpressCCIX IP, supporting CCIX™ or Cache Coherent Interconnect for Accelerators (X). The decision to support CCIX is fueled by an increasing demand for higher throughput for PCIe-based systems, driven largely by enterprise and data center customers.
The CCIX Consortium has developed the Cache Coherent Interconnect for Accelerators (X) protocol to enable a new class of interconnect focused on emerging acceleration applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology.
In addition to their core business of licensing PCIe semiconductor IP, PLDA has a long history of robust hardware designs. PLDA initially built its first PCIe 4.0 platform, Gen4SWITCH, as a way to demonstrate the PCIe 4.0 technology and to test designs at PCIe 4.0 speed for its own needs. Widely used during tradeshows and at PCI-SIG workshops as an early PCIe 4.0 host platform, Gen4SWITCH has become a star product in high demand, and has spawned a complete Test and Validation product line, targeted specifically at the needs of PCIe 4.0 SoC designers and system vendors.
PLDA has leveraged their extensive PCIe expertise to provide a comprehensive suite of Test and Validation solutions for the PCI Express protocol, enabling faster and more affordable validation of PCIe silicon and devices
Check the video demonstration of Inspector.
Inspector is a PCI Express 4.0 Host Platform for diagnostic and performance tuning of PCIe 4.0 silicon, devices,and software.
- Diagnose PHY and link issues pre-L0 and post-L0
- Test your lane margining circuitry
- Verify and tune the performance of your PCIe 4.0 devices in a x86 environment
- Develop and test your application software on an early PCIe 4.0 x86 platform
GOWIN Semiconductor selects PLDA XpressRICH3 Controller IP as the PCIe interface block in their FPGA product line
SAN JOSE, Calif., February 27, 2018 – PLDA®, the industry leader in PCI Express® interface IP solutions, today announced that GOWIN Semiconductor, a leading semiconductor company in China, has chosen PLDA’s PCIe ASIC IP for their upcoming FPGA product line. GOWIN offers a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits.
Debugging issues in a PCIe system is often challenging and time consuming. PCIe Express is a complex protocol with little or no visibility on problems that have a long-term impact.
PLDA is releasing a series of tutorials that explains the role of each debug tool and method in troubleshooting issues, with simple tips and use cases.