TSMC SYMPOSIUM NA 2019 - Tuesday, April 23
Santa Clara Convention Center
Come and meet the PLDA Team at TSMC Symposium North America show in Santa Clara!
This free event provides a great opportunity for you to discover PLDA's latest High Speed Interconnect solutions, such as :
In this video, we show how SoC designers can leverage the vDMA engine built into PLDA’s XpressRICH-AXI PCIe controller to manage concurrent high performance data traffic between a virtualized PCIe device and multiple Virtual Machines running on the host platform.
1. Introduction
Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.
In this article, we look into the various protocols by providing a brief history, a quick technical comparison, and the latest deployment status. We also offer our perspective on the evolution of these protocols.
The explosion in data traffic due to the advent of Artificial Intelligence, machine learning, automotive and IoT prompts for new System-on-Chip architectures that allow system developers to build high-performance applications that are able to ingest and process huge amounts of heterogeneous data.
1. Introduction
As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc.
The transition to PCIe 4.0 and 5.0 with increasing PCIe signaling speeds (16GT/s and 32GT/s) also augments the risk of errors due to tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g. crosstalk, line attenuation, jitter, etc.).
Shanghai, China—Dec 11, 2018
Brite Semiconductor (“Brite”), a world-leading ASIC design service and DDR controller/PHY IP provider headquartered in Shanghai, China, today announced their collaboration with Naneng Microelectronics and PLDA to deliver a complete PCIe 2.0/3.0 solution based on SMIC’s 40nm and 55nm process technology.
Guosheng Wu, CEO of Naneng Microelectronics, said, “Collaboration between Naneng and Brite can effectively reduce the risks and costs of SoC design by providing a low power consumption and small-area PCIe-2.0/3.0 solution based on SMIC’s 40nm and 55nm process, that meets the latest PIPE specifications and supports 2.5G and 5G data rate. We are looking forward to working with Brite to provide customers with a global solution that offers high performance and low cost, while complying with the relevant standards.”
PLDA, the industry leader in PCI Express® controller IP solutions and Samtec, a privately held $800MM global manufacturer of a broad line of electronic interconnect solutions, today announced a demo of their combined PCIe 4.0 solution that delivers full PCIe 4.0 bandwidth (16 GT/s) over copper or optical fiber at minimal cost.
The solution is based on a PLDA PCIe 4.0 acquisition board running PLDA’s PCIe 4.0 controller IP combined with Samtec’s FireFly™ Micro Flyover System™. This demo suggests a solution to overcoming the inherent limitations of maintaining PCIe 4.0 performance over long distances without changing the motherboard technology or using costly retimers.
SAN MATEO, Calif., Nov. 26, 2018 -- SiFive, the leading provider of commercial RISC-V processor IP, today announced that PLDA, the leader in PCIe and CCIX Controller IP solutions has joined the DesignShare™ ecosystem. Through this collaboration, PLDA will provide its rich suite of XpressRICH core IP that enables high-speed connectivity solutions for many applications like enterprise storage, networking, high-performance computing and artificial intelligence to name a few.
As cloud computing and deep learning accelerators drive faster advances in the PCIe roadmap, existing hardware designs cannot support the higher speed signals over the same distances. The PCIe 1.0 specification allowed signals to travel as much as 20 inches over traces in mainstream FR4 boards, even while passing through two connectors. In contrast, today’s quicker 16 GT/s PCIe 4.0 signals will peter out in under six inches and without going over any connectors.
ICCAD China 2018 - November 29-30
Zhuhai International Convention & Exhibition Center
Come and meet the PLDA Team at CSIA-ICCAD 2018 Annual Conference & Zhuhai IC Industry Innovation and Development Summit show in Zhuhai !
This free event provides a great opportunity for you to discover PLDA's latest PCIe solutions, such as :
